Test plan generation for analog integrated circuits

Details Test plan generation for analog integrated circuits Test plan generation for analog integrated circuits

1993-02-05

1994-11-29

Harvey, Jack B.

Boots, shoes, and leggings

364578, 364481, 324 731, 3241581, G05B 1902

Patent

active

053696042

ABSTRACT:
A method of generating a test plan for a circuit designed with blocks of analog, digital, or mixed signal components. Each block is treated as a separate functional unit, with a test having block inputs that are set to predetermined values. A matrix of circuit equations is set up to determine what circuit inputs will result in these block inputs. The required number of equations is obtained by identifying any circuit inputs that need to be set heuristically.

REFERENCES:
patent: 4000460 (1976-12-01), Kadakia et al.
patent: 4204633 (1980-05-01), Goel
patent: 4228537 (1980-10-01), Henckels et al.
patent: 4656632 (1987-04-01), Jackson
patent: 4907230 (1990-03-01), Heller et al.
patent: 5105373 (1992-04-01), Rumsey et al.

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