Test pin for a printed circuit board

Details Test pin for a printed circuit board Test pin for a printed circuit board

1999-07-26

2001-09-11

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06288562

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to the testing of printed circuit boards and, more particularly, to a test pin for providing test probe access to a multi-layer printed circuit board.
With advances in the miniaturization of surface mount printed circuit components, it is becoming more difficult to connect test probes to printed circuit assemblies. Traditionally, test connections were made to an integrated circuit package by using a spring loaded clip device that fit over the integrated circuit package and made contact with its mounting legs which provide connections to the integrated circuit within the package. With the advent of ball grid array integrated circuit packages and other small parts that have their interconnection underneath their package bodies, this is no longer possible. Accordingly, a need exists for providing test probe access for such a circuit package.
Modern printed circuit boards are typically a laminate of multiple layers each having circuit traces thereon. Small plated through-holes, called vias, are used to interconnect the printed wiring traces from one layer of the board to another. These vis are also used for manufacturing test purposes and typically have a ten mil finished inside hole diameter, which is usually filled with solder during the manufacturing process. It would be desirable to be able to utilize the vias for obtaining test probe access.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a conductive test pin for use with a multi-layer printed circuit board having a plated via interconnecting circuit traces on two layers of the board. The test pin comprises a first straight part adapted to extend through the via in contact with the via plating and a second part formed into a loop for engagement by a test probe clip. The loop is dimensioned larger than the via so that the loop remains outside the via.
A method according to the present invention provides test probe access to a plated via in a multi-layer printed circuit board. The method comprises the steps of providing a conductive test pin having a first straight part and a second part formed into a loop, applying heat to the via, adding solder to the via, inserting the test pin straight part into the via, and removing heat from the via.


REFERENCES:
patent: Re. 36442 (1999-12-01), Kardos
patent: 4806856 (1989-02-01), Hvezda et al.
patent: 5833479 (1998-11-01), Talbot

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