Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-06-05
2003-07-22
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
C430S030000
Reexamination Certificate
active
06596552
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of semiconductor manufacturing and, more particularly, to a method and apparatus for monitoring and evaluating effects of electrostatic discharge associated with semiconductor manufacturing.
BACKGROUND OF THE INVENTION
The manufacturing of complex semiconductor devices involves a series of processes including deposition, photolithography and etching. During the photolithography process, semiconductor manufacturers often use a photomask to copy an image of an electronic circuit onto a semiconductor wafer. Photomasks come in various sizes and shapes such as 1× and 2×photomasks or 2×, 2.5×, 4×, and 5×reticles. Reticles are a type of photomask that can be shot several times onto a single wafer with a photolithographic tool known as a stepper or scanner. Photomasks generally include a quartz blank having a patterned metal layer (e.g., chrome) deposited on one surface. This patterned metal layer contains the microscopic image of the electronic circuit, which is frequently referred to as the photomask's geometry.
The quality of this geometry will substantially dictate the quality of the electronic circuits formed on the semiconductor wafers from the photomask. As design rules have moved toward smaller and more dense integrated circuit (IC) devices, the integrity of the photomask geometry has become increasingly important. One key cause of geometry degradation is electrostatic discharge (ESD). ESD is created when a force causes a charge imbalance among a photomask's chrome structures. In the photomask context, effects of ESD include material sputtering and material migration. Instances of these effects can result in the non-functioning of IC devices created from the degraded photomask. As such, an incentive exists for identifying problem photomasks and potential sources of ESD. Unfortunately, given the large number of process steps necessary to create a large scale integrated circuit (IC) device, it is often very difficult to identify and monitor ESD effects throughout the complete manufacturing process. This is especially true when photomask production and photolithographic tool manufacturing are included in the list of semiconductor manufacturing process steps.
One conventional method of testing for ESD damage on wafers is the inclusion of a test die on a reticle. This method retroactively identifies ESD effects. With this method a test die is included among a number of actual dies. The test die contains a simplified geometry that allows for process control and monitoring during wafer fabrication. However, the test die method requires the production of a bad wafer before a problem is detected. Moreover, the simplified test die geometry may not necessarily approximate the design rule to which the actual IC devices are manufactured. In addition, the test die may not provide information about actual reticle quality.
Defect inspection is another conventional method of testing that which focuses more on the photomask. Defect inspection comprises either a die-to-die inspection or die-to-database inspection. In either case, an actual photomask geometry is compared against an ideal photomask geometry. Differences between the actual and the ideal are identified and a determination as to defect severity is made. Again, the inspection method is retroactive in that it identifies bad dies after they have become bad. Moreover, the inspection method requires a costly device operable to compare the actual geometry with the ideal geometry.
A further method includes the taking of electrical field strength measurements while a photomask is stored, being handled, being shot or exposed during a photolithographic process. This is problematic for at least two reasons. First, electrical field strength measurements are not ESD measurements. The strength of an electrical field is merely an indicator of ESD potential. And second, the measurement is only an indicator of the ESD potential associated with the photolithographic process (i.e., an indicator of only one component of the total ESD effects a typical photomask encounters).
SUMMARY OF THE INVENTION
In accordance with teachings of the present invention, a method and apparatus for monitoring and evaluating effects of electrostatic discharge (ESD) associated with semiconductor manufacturing are provided. The disclosed invention provides significant advantages over prior technologies for ESD detection and evaluation.
According to one aspect of the present invention, a test photomask, which may be any variety of photomask (e.g., a reticle), that contains an ESD sensitive geometry may be exposed to a single or a variety of semiconductor manufacturing procedures. The test photomask may also be exposed to various pieces of equipment related to manufacturing semiconductors. After exposure, the test photomask is analyzed to determine how much, if any, degradation of the geometry has occurred as a result of the exposure. An ESD sensitive geometry may be designed in accordance with teachings of the present invention such that it is significantly more sensitive to ESD than a typical photomask geometry for producing IC devices. In addition, an ESD sensitive geometry may be formed in accordance with the present invention to accurately relate to various design rules including the design rule to which a specific IC device will be manufactured.
Technical advantages of the present inventions include providing a test photomask containing a highly ESD sensitive geometry. The highly sensitive ESD geometry allows the test photomask to reveal ESD effects in one or more cycles of exposure to a given manufacturing procedure or manufacturing device whereas a photomask used to manufacture IC devices may not reveal similar effects until after hundreds or thousands of exposures.
Further technical advantages of the present invention include providing an ESD sensitive geometry, which may be specifically designed to relate to one or more given design rules for IC manufacturing. The ability to relate to multiple design rules allows a manufacturer to quickly determine to what design rule it can consistently manufacture with its current system.
Additionally, a test photomask incorporating teachings of the present invention may be relatively easy and inexpensive to read and may allow users to identify, monitor and evaluate a single aspect or procedure of a semiconductor manufacturing process which may include the mask shop process. Alternatively, the user may identify, monitor and evaluate the entire process for cumulative ESD effects. This ability allows the user to quickly identify ESD problem areas.
Other technical advantages will be apparent to one of skill in the art from the description, drawings and claims.
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Pert Evan
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