Test pattern structure for endurance test of a flash memory devi

Static information storage and retrieval – Floating gate – Particular connection

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36518533, 3651851, 257316, 257319, 257321, 257 48, G11C 2900

Patent

active

058645012

ABSTRACT:
This invention relates to a test pattern structure comprising a test pattern structure for endurance test of a flash memory device comprising: at least three active regions formed on a semiconductor substrate, each active region being isolated by a field oxide film; a common drain region formed on each active region, respectively; source regions formed on left and right sides of the common drain region in each active region, respectively; a first common floating gate formed along left side of each common drain region; a second common floating gate formed along right side of each common drain region; a control gate overlapped with the first and second floating gates, respectively and connected from each other at both ends of the first and second floating gates; a select gate formed over the common drain region, the source regions and the control gate in each active region, respectively; and metal wires connected to the common drain region, the source regions and the control gate in each active region, respectively.

REFERENCES:
patent: 5255219 (1993-10-01), Sakai
patent: 5615150 (1997-03-01), Lin et al.

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