Test pattern selection method for testing of integrated circuit

Details Test pattern selection method for testing of integrated circuit Test pattern selection method for testing of integrated circuit

1997-03-27

1998-12-01

Chung, Phung M.

Excavating

371 36, G06F 1100

Patent

active

058449094

ABSTRACT:
The invention provides a test pattern selection method for testing of an integrated circuit which can achieve a high fault coverage using a small number of patterns and minimizes the total testing time. From within a test pattern file which includes L test patterns, N test patterns are read out as a set of temporarily selected patterns, and a fault coverage according to the combination of the N temporarily selected patterns is calculated. Then, one of the other test patterns is successively substituted into one of the N temporarily selected patterns and a fault coverage is calculated for each combination of test patterns. Then, N test patterns of a combination which exhibits the highest one of the fault coverages calculated in this manner are determined as finally selected patterns.

REFERENCES:
patent: 4891812 (1990-01-01), Bocci et al.
patent: 5619509 (1997-04-01), Maruyama et al.
Ravi k. Gulati et al., "Detection of undetectable faults using IDDQ testing", International Test Conference 1992, pp. 770-777.

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