Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2006-04-18
2006-04-18
Clark, S. V. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S758000
Reexamination Certificate
active
07030507
ABSTRACT:
Disclosed is a test pattern comprising: lower metal patterns for test formed in such a manner that crank-type patterns are arranged in sequence overlapping on each other in a view along a vertical line; hole patterns formed in such a manner that each of the hole patterns exposes either a front end and a rear end of each crank-type lower metal pattern; and upper metal patterns formed in such a manner that each upper metal pattern interconnects a front end of each lower metal pattern and a rear end of an adjacent lower metal pattern overlapping on each other in a view along a vertical line.
REFERENCES:
patent: 3922707 (1975-11-01), Freed et al.
patent: 6042933 (2000-03-01), Hirai et al.
patent: 6232619 (2001-05-01), Chen et al.
patent: 6559475 (2003-05-01), Kim
patent: 6577149 (2003-06-01), Doong et al.
patent: 6787800 (2004-09-01), Weiland et al.
Clark S. V.
Hynix / Semiconductor Inc.
Ladas & Parry LLP
LandOfFree
Test pattern of semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test pattern of semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern of semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3539668