1991-02-14
1993-11-23
Beausoliel, Jr., Robert W.
Excavating
G06F 1100
Patent
active
052651029
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a test pattern generator which generates test patterns for testing semiconductor integrated circuits.
BACKGROUND ART
A test pattern generator forms a part of an IC tester for testing semiconductor ICs and generates a test pattern to be applied to the IC under test and an expected value pattern for comparison with a response from the IC under test. These two patterns are commonly referred to simply as a test pattern.
A conventional test pattern generator is shown in FIG. 1. A clock PCK for pattern generating use and a start signal S are applied to an address generating circuit 11 and an address provided therefrom is used to read out a test pattern memory 12 in which a test pattern has been stored. The test pattern memory 12 is usually constituted by an SRAM (i.e. a static RAM).
A large-capacity test pattern memory is needed to cope with extended test patterns which result from an increased degree of integration of circuits to be tested and an automatic generation of test patterns by a computer. Conventionally, such a large-capacity test pattern memory employs the SRAM, and hence is expensive.
The number of transistors necessary for forming one memory cell is four to six in the case of the SRAM but only one in the case of a DRAM (i.e. a dynamic RAM). In the case of fabricating IC memories of the same chip area through a patterning process under the same rule, the IC memory using the DRAM is larger in capacity and lower in the unit cost per bit than the IC memory using the SRAM. Hence, the use of the DRAM will cut the manufacturing cost of the test pattern memory. However, stored contents of the DRAM will disappear unless refreshed at regular time intervals, and during the refresh the readout of a test pattern is suspended, making high-speed pattern generation impossible. On this account, the prior art does not employ the DRAM for the test pattern memory.
The present invention is to provide a test pattern generator which can be fabricated at low cost through use of the DRAM and is capable of generating test patterns at high speed.
DISCLOSURE OF THE INVENTION
According to the present invention, a control circuit, which operates on a system clock, is controlled by a start signal and a full flag to generate an address generating clock, a readout control signal and a write clock and, at the same time, a refresh control circuit is periodically provided from the control circuit. An address generating circuit is controlled by the address generating clock from the control circuit to generate an address. A test pattern memory formed by the DRAM and having stored therein test patterns is read out, based on the address from the address generating circuit and the readout control signal from the control circuit, and at the same time, the test pattern memory performs a refreshing operation based on the refresh control signal provided from the control circuit. The test pattern read out from the test pattern memory is written into a FiFo memory by the write clock from the control circuit. When filled with test patterns, the FiFo memory provides a full flag to the control circuit and the test patterns are read out from the FiFo memory in synchronism with the pattern generating clock. The address generating clock is made higher in rate than the pattern generating clock.
When the FiFo memory becomes full, the readout of the test pattern is started, and when the full flag falls, the address generating clock, the readout control signal and the write clock are produced and then the test pattern memory is read out. The test pattern thus read out is written into the FiFo memory and the refresh control signal is produced. Even while the test pattern memory performs the refreshing operation based on the refresh control signal, the readout of the test pattern from the FiFo memory is continued. Upon completion of the refreshing operation, the readout of the test pattern memory is resumed and the test pattern read out therefrom is written into the FiFo memory. Consequently, test pat
REFERENCES:
patent: 3982111 (1976-09-01), Lerner et al.
patent: 4622668 (1986-11-01), Dancker et al.
patent: 4782487 (1988-11-01), Smelser
patent: 4827476 (1989-05-01), Garcia
patent: 4980888 (1990-12-01), Bruce et al.
patent: 5091910 (1992-02-01), Ochi
patent: 5127010 (1992-06-01), Satoh
Advantest Corporation
Beausoliel, Jr. Robert W.
Chung Phung M.
LandOfFree
Test pattern generator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test pattern generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern generator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1855516