1997-09-08
1998-12-15
Nguyen, Hoa T.
Excavating
371 275, G11C 2900, G01R 3128
Patent
active
058504028
DESCRIPTION:
BRIEF SUMMARY
This application is a 371 of the PCT/JP96/00037, filed on Dec. 01, 1996.
TECHNICAL FIELD
This invention relates to a test pattern generator for testing semiconductor devices under test, and more particularly, to a test pattern generator which simplifies the generation of expected data, generation of which tends to be complex.
BACKGROUND ART
FIG. 2 shows an example of a semiconductor test system in a conventional technology for testing whether the devices under test are defective or not. The example of FIG. 2 shows a case in which devices to be tested are semiconductor memories. A data signal is provided from a data generator A14 to a memory device under test. A mask data signal which prohibits the data signal from entering the memory device under test is provided from the data generator B15. By a wave formatter 2, the data and mask signals are shaped their waveforms and supplied to the memory 3 under test. An address signal is provided from an address generator 13. Each of the generators noted above performs the data generation based on the instructions from an instruction memory 12. The instruction memory 12 is controlled by a program counter 11. The test pattern generator 10 is comprised of the above noted respective generators, the instruction memory, and the program counter.
Next, the data that has been read-out from the memory device 3 under test is compared with an expected data signal from the data generator A14 by a logic comparator 4. The performance of the memory device 3 under test is evaluated by comparing whether the data from the memory device 3 coincides with the expected data.
Among semiconductor memories, there exists a type of memory device that can perform a write enable and/or disable control for each data bit. For writing data in this type of semiconductor memory device, write mask data having the same number of bits as that of write data are applied to the memory device together with the write data. Only when the write mask data corresponding to the memory bit is "1", the data in the memory bit is renewed. FIG. 3 shows an example of process for writing the data in such a semiconductor memory device when the bit width of the memory device is four (4). In this example, the write mask data is #E, and thus, the write data for the memory bits "1", "2" and "3" are renewed. For the memory bit "0", the previous data is maintained without change.
To test the semiconductor memory devices that can control its write enable and/or disable for each data bit as explained above, many test pattern generators include two systems of data generators (14, 15). When writing the data, one data generator is used for generating the write data while the other data generator is used for generating the write mask data. When reading the data from the memory, one of the data generators is used for generating expected value data. The data generator is arbitrarily selected and is connected to the logic comparator 4.
FIG. 4 shows an example of operation in the conventional technology. The example of FIG. 4 shows the case where initialization data from the data generator A is expressed as #3. In the initialization step, all of the memory bits must be write enable, and thus the write mask data from the data generator B shows #F. Hence the data #3 is written in the memory device under test as the initialization data.
In the write step, the write data from the data generator A in this example is #C. The write data corresponds to the inverse data of the initialization data (#3). The write mask data from the data generator B in this case is #E. Hence, in the memory device under test, data "0" is written in the memory bit 1, data "1" is stored in the memory bit 2, data "1" is stored in the memory bit 3. Since the write mask data for the memory bit 0 is "0", the initial data of "1" is unchanged. As a result, the data #D is stored in the memory device under test.
In the read step, data identical to the data #D in the memory device under test have to be generated by the data generator A as expected value data. In other w
REFERENCES:
patent: 4670879 (1987-06-01), Okino
patent: 4862460 (1989-08-01), Yamaguchi
patent: 4876685 (1989-10-01), Rich
patent: 5668819 (1997-09-01), Fukushima
patent: 5673271 (1997-09-01), Ohsawa
patent: 5751738 (1998-05-01), Shimura
Advantest Corp.
Nguyen Hoa T.
LandOfFree
Test pattern generator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test pattern generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern generator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1463119