Test pattern generation for an electronic circuit using a transf

Details Test pattern generation for an electronic circuit using a transf Test pattern generation for an electronic circuit using a transf

1995-01-18

1996-06-18

Canney, Vincent P.

Excavating

39518309, G06F 1110

Patent

active

055286046

ABSTRACT:
Test pattern generation for a sequential logic circuit having combinational logic elements and sequential elements (D flip-flops) is enhanced in generation time and test pattern quality by first transforming the circuit to simplify the circuit for test pattern generation. In one embodiment the retiming transformation is used in which sequential elements are moved across combinational logic elements to increase the ratio of the total number of states which are traversable, and thus simplify the circuit for test pattern generation. The test set generated is equally applicable to the transformed test circuit as well as the manufactured circuit.

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Lee et al., "Hope: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits," Proc. of the 29th ACM/IEEE Design Auto. Conf., 1992, pp. 336-340.

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