Excavating
Patent
1995-10-19
1997-03-25
Beausoliel, Jr., Robert W.
Excavating
371 211, G06F 1100, G11C 2900
Patent
active
056152183
ABSTRACT:
A test pattern generation device for testing semi-conductor devices is presented. The device generates high capacity patterns much more quickly than is possible with the conventional test pattern generator while permitting the use of the conventional layout of the test patterns and the common operational features of the existing test pattern generators. The control circuit stores an index address in the address pointer. Upon receiving a transfer command, the index is outputted to the execution memory, and the leading address data thus read out is stored in the modifier register. Next, the address generator is activated, and the address data and the output of the modifier register are added by the adder. The added result is inputted into the execution memory via the selector. This process is repeated successively for other leading address data, and the test patterns are thus outputted from the execution memory without the use of a buffer memory used in the conventional types of test pattern generators.
REFERENCES:
patent: 4293950 (1981-10-01), Shimizu et al.
patent: 5337045 (1994-08-01), Shirasaka
patent: 5473616 (1995-12-01), Tsutsui et al.
Ando Electric Co. Ltd.
Beausoliel, Jr. Robert W.
Tu Trinh L.
LandOfFree
Test pattern generation device for semiconductor testing apparat does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test pattern generation device for semiconductor testing apparat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern generation device for semiconductor testing apparat will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2210251