Test pattern generation

Details Test pattern generation Test pattern generation

1992-10-28

1995-02-14

Voeltz, Emanuel T.

Excavating

36457104, 364580, G06F 1128

Patent

active

053901932

ABSTRACT:
A method for generating and simulating test patterns to detect faults (57, 63) in an integrated circuit. The method comprises identifying all nets (27) which can potentially be shorted together. Each potential fault (34, 36, 37, 38, 39) is categorized as either a feedback fault or a non-feedback fault. A test pattern is generated to detect the selected potential fault. The test pattern is simulated to determine which additional potential faults are detected by the test pattern. Potential faults which are detected by the test pattern are deleted from the fault list (12). The method is repeated until no potential faults remain on the fault list (12).

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"Accurate Modeling & Simulation of Bridging Faults", S. Millman et al., Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, May 1991, San Diego, Calif.
"An Accurate Bridging Fault Test Pattern Generator", S. Millman et al., Proceedings of the IEEE International Test Conference, Oct. 1991, Nashville, Tenn. pp. 1-8.
"Fault Model Evolution For Diagnosis: Accuracy vs. Precision", S. Millman et al., IEEE 1992 Custom Integrated Circuits Conference, May 1992, Boston, Mass., pp. 1-4.

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