Test pattern generating apparatus and method

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Details

39518301, G06F 1100

Patent

active

057198810

ABSTRACT:
A test pattern generating apparatus including circuit information/fault information input means 101, test pattern input generating means 102, test pattern input assigning means 103, logical simulation means 104, fault defining means 105, fault simulation means 106, fault extracting(detecting) means 107, initial test pattern extracting means 108, test pattern converting means 109 for assigning undefined values to an initial test pattern, final test pattern extracting means 110, test pattern generation judging means 111, all extracted test pattern merging means 112, and merged test pattern output means 413.

REFERENCES:
patent: 4862071 (1989-08-01), Sato et al.
patent: 4870345 (1989-09-01), Tomioka et al.
patent: 5463639 (1995-10-01), Koishi et al.

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