Test pattern generating apparatus

Details Test pattern generating apparatus Test pattern generating apparatus

1992-08-28

1995-07-18

Beausoliel, Jr., Robert W.

Excavating

371 151, 364579, G06F 1100, G01R 3128

Patent

active

054348692

ABSTRACT:
A test pattern generating apparatus for generating test patterns to test a sequential circuit having at least one memory element. The apparatus calculates, in response to a primary input applied to the sequential circuit, analog logic values for signal lines in the sequential circuit using a nonlinear function, then stores history data for the analog logic values with an inverse covariance matrix of the analog logic values. The apparatus then calculates an evaluation value according to the degree of variance between the analog logic values and the history data. A primary input setting unit is used for producing a next primary input which provides a maximum evaluation value from the evaluation value obtained from the present primary input. inputs produced by the primary input setting unit.

REFERENCES:
patent: 4317200 (1982-02-01), Wakatsuki et al.
patent: 4754215 (1988-06-01), Kawai
Cheng et al., "A Simulation-Based Method for Generating Tests for Sequential Circuits", IEEE Transactions on Computers, Dec. 1990, pp. 1456-1463.
Wirtz, "CrossCheck: An ASIC Testability Solution", CrossCheck Technology, Inc. 1990 IEEE, pp. 444-448.
Brglez et al., "Combinational Profiles of Sequential Benchmark Circuits", Mictroelectronics Center of North Carolina, ISCAS '89, 1989 IEEE, pp. 1929-1934.
Tsu-Wei Ku, et al. "A Sequential Test Generator with Explicit Elimination of Easy-To-Test Faults", Proceedings International Test Conference, pp. 83-87 (1991).

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