Test pattern generating apparatus

Excavating

Patent

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Details

324 73R, 371 27, G06F 1100, G01R 3128

Patent

active

042939500

ABSTRACT:
A test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory control signal being applied to a memory under test. The address pattern is provided to an area inversion control signal generation section to produce an inversion control signal corresponding to the address pattern, by which the data pattern may be inverted and then outputted.

REFERENCES:
patent: 3751649 (1973-08-01), Hart, Jr.
patent: 3969618 (1976-07-01), Strubel et al.
patent: 4066882 (1978-01-01), Esposito
patent: 4168527 (1979-09-01), Winkler

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