Test pattern generating apparatus

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G01R 3128

Patent

active

045861811

ABSTRACT:
A test pattern generator includes means for reading out a plurality of memories non-successively while outputting the test patterns stored identically in the addresses of the memories, such as for sequentially repeating the test patterns that are provided to a logic circuit being tested. The sequence of test patterns is determined by a series of instructions which are accessed by a program counter, and the instructions can cause a jump in the counting of the program counter, for instance to repeat addresses of the memories for repeating a desired sequence of test patterns a predetermined number of times. The timing of the addressing of the memories for the reading out of the test patterns can be faster than the timing for writing the test patterns into the memories for storage.

REFERENCES:
patent: 4287594 (1981-09-01), Shirasaka
patent: 4313200 (1982-01-01), Nishiura
patent: 4402081 (1983-08-01), Ichimiya et al.
patent: 4450560 (1984-05-01), Conner

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