Test pattern for monitoring metal corrosion on integrated...

Chemistry: analytical and immunological testing – Process or composition for determination of physical state... – Surface area – porosity – imperfection – or alteration

Reexamination Certificate

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C436S006000, C436S001000, C430S007000, C324S1540PB, C029S846000, C029S847000

Reexamination Certificate

active

06261843

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to the use of wafers having metal test patterns to monitor the metal corrosion susceptibility of integrated circuit wafers. More particularly this invention relates to a comparison of numbers of defects per unit area of test pattern wafers, which are processed with product wafers, before and after the test pattern wafers are subjected to a stress environment.
(2) Description of the Related Art
U.S. Pat. No. 5,411,890 to Falat describes using a tapered metal strip on a transparent substrate to monitor corrosion. Corrosion causes the boundary between reflective and non reflective regions to move across the substrate. This test site is quite different than that described in this invention.
U.S. Pat. No. 5,389,216 to Balkanli describes a method of detecting corrosion in underground pipes. The method uses an analysis of the response to injected current pulses to evaluate corrosion.
U.S. Pat. No. 5,481,198 to Patel measures the resistance of a buried neutral wire of underground electrical cables by injecting additional current into the wire and measuring the voltage drop across a known length. This measured resistance is used to determine the amount of corrosion of the underground cable.
U.S. Pat. No. 5,159,752 to Mahant-Shetti et al. uses a grid pattern of electrodes deposited on a semiconductor wafer to monitor corrosion. An electron beam is directed on the structure and a scanning electron microscope is used to observe emitted secondary electrons. The observed secondary electrons gives a picture related to the condition of the pattern, such as shorts, opens, etc. A stress environment is not used to accelerate corrosion.
The invention of this patent application uses a number of test patterns to simulate contact regions, electrode regions, and bulk metal regions. A stress environment is used to accelerate corrosion. The numbers of defects per unit area are measured before and after the test pattern wafers are subjected to the stress environment. A comparison of the numbers of defects per unit area before and after the test pattern wafers are subjected to the stress environment is used to monitor metal corrosion susceptibility of production wafers.
SUMMARY OF THE INVENTION
In the manufacture of integrated circuit wafers corrosion of metal elements, such as metal electrodes, metal contacts, or other metal features, can cause serious problems. Often this metal corrosion is the result of parts of the manufacturing process which have gone out of control thereby exposing the metals to an excess of chloride ions or the like. These conditions can affect a large number of product wafers before the corrosion becomes noticeable thereby compounding the problem of finding and correcting the process problem with the necessity of discarding a large number of product wafers.
It is an objective of this invention to provide a method of determining if a corrosion problem is present at the point of the process where corrosion problems are introduced thereby simplifying the problem of correcting the process problem and avoiding the necessity of discarding product wafers.
It is a further objective of this invention to provide a test device for use in determining if a corrosion problem is present at the point of the process where corrosion problems are introduced thereby simplifying the problem of correcting the process problem and avoiding the necessity of discarding product wafers.
This objectives are achieved by using specially designed test patterns on test wafers which can detect different types of corrosion, such as metal electrode sidewall corrosion, metal contact corrosion, or the like. These test wafers are processed with product wafers until the appropriate process point. The test patterns are then analyzed using a means for determining the number of defects per unit area for the test pattern and a first number of defects per unit area is stored. The test wafers are then exposed to environmental stress conditions, such as elevated temperature and relative humidity, for a period of time.
The test patterns are then analyzed a second time and a second number of defects per unit area is determined. Then the difference between the second number of defects per unit area and the first number of defects per unit area is compared with an allowable number of defects per unit area. If the difference between the second number of defects per unit area and the first number of defects per unit area is less than the allowable number of defects per unit area processing of the product wafers continues. If the difference between the second number of defects per unit area and the first number of defects per unit area is equal to or greater than the allowable number of defects per unit area processing of the product wafers is stopped until the process problems are corrected and continued production of defective wafers is avoided. Due to the design of the test patterns an analysis of the type of corrosion can be used to help determine the problems causing metal corrosion and the point in the process where the problems are occurring.


REFERENCES:
patent: 5159752 (1992-11-01), Mahant-Shetti et al.
patent: 5389216 (1995-02-01), Balkanli
patent: 5411890 (1995-05-01), Falat
patent: 5481198 (1996-01-01), Patel

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