Test pattern address generator

Details Test pattern address generator Test pattern address generator

1981-05-26

1984-01-31

Smith, Jerry

Excavating

G06F 1122

Patent

active

044293895

ABSTRACT:
A test pattern generator is used for generating a series of address signals such as for exercising an integrated circuit memory. Master reference clock means are used to trigger a three stage counting circuit and also a circuit array of exclusive OR gates. The outputs of the stages of the counter provide individual inputs to each of the exclusive OR gates. The array of exclusive OR gates is arranged so that each exclusive OR gate has an output line which provides one bit of information for the address signals. The combination of the outputs of the OR gates forms a parallel bus which carries the address signals to be applied to the integrated circuit memory. The circuit generates a specialized address pattern in which the original address generated is complemented, then incremented on a series of increment-complement actions so that all combinations of the row and column drivers in the integrated circuit memory are exercised.

REFERENCES:
patent: 4195770 (1980-04-01), Benton et al.
patent: 4204633 (1980-05-01), Goel
patent: 4263669 (1981-04-01), Staiger
patent: 4271512 (1981-06-01), Lylus
patent: 4332028 (1982-05-01), Joccotton et al.

Affiliated with

Also associated with

Rating

Test pattern address generator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test pattern address generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern address generator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2349384