Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-04-06
2002-06-18
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S755090, C439S073000
Reexamination Certificate
active
06407566
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the testing of integrated circuit devices assembled into a multi-chip module. Specifically, the present invention relates to an apparatus, and a method of using the same, for testing integrated circuit packages in a simulated multi-chip module environment.
2. State of the Art
Some types of integrated circuit devices are generally comprised of a semiconductor die attached to a lead frame. The lead frame includes a plurality of conductive leads, or lead fingers. Disposed on an active surface of the semiconductor die is a plurality of bond pads. At least one of the bond pads is electrically coupled to at least one lead finger of the lead frame. Typically, multiple bond pads on the semiconductor die are each electrically coupled—by, for example, a wire bond—to a lead finger. An encapsulant material, such as plastic or ceramic, encases the semiconductor die and a portion of the lead frame to form an integrated circuit (IC) package.
A portion of each of multiple lead fingers of the lead frame extends from the encapsulant material of the IC package of this type to provide external leads for electrically connecting the IC package to other devices. An IC package will generally have multiple external leads extending from at least one surface of the IC package. During fabrication and after encapsulation of the semiconductor die, the external leads are commonly subjected to a trim and form operation in which the external leads may be cut, bent, or otherwise shaped to form a specified configuration. The external leads are usually arranged in a specified pattern, or footprint. One conventional IC package—the small-outline J-lead (SOJ) package—includes external leads that are formed into a hook, or J-shaped, configuration. Many other conventional IC package configurations utilizing lead frame construction are known in the art, such as, for example, the thin small-outline package (TSOP). Methods of fabricating IC packages employing lead frames are well known in the art.
Integrated circuit packages are commonly assembled into multi-chip modules for connection to higher-level packaging, such as a motherboard or a personal computer chassis. Generally, a multi-chip module includes a carrier substrate, such as a printed circuit board, having a plurality of IC packages mounted thereto. Other electrical components, such as resistors, capacitors, inductors, or other suitable devices, may also be mounted on the carrier substrate of the multi-chip module, or even on the IC packages. Electrical communication among the IC packages, between the IC packages and other electrical components on the multi-chip module, and between the IC packages and external devices, is established by conductors on the multi-chip module carrier substrate. The conductors may be conductive traces fabricated on the surface of, or internal to, a printed circuit board. Methods for fabricating printed circuit boards having conductive traces, as well as other types of substrates having conductors thereon, are well known in the art.
The conductors on a multi-chip module substrate may include ends, or contact pads, arranged in a number of contact pad arrays. Each contact pad array includes a plurality of contact pads arranged in a pattern corresponding to the footprint of the IC package intended to be mounted on that contact pad array. Soldering, conductive epoxy, or any other suitable process may be used to permanently attach, and electrically connect, the external leads of an IC package to associated contact pads of an array on a multi-chip module. Methods for permanently attaching and electrically connecting IC packages to substrates are well known in the art. Typically, an assembled multi-chip module includes a plurality of IC packages, wherein each of the IC packages is permanently attached to a contact pad array on a surface of the multi-chip module. By way of example only, a multi-chip module may be a memory module comprised of a carrier substrate having opposing surfaces, with one or both of the opposing surfaces of the carrier substrate including multiple contact pad arrays and a plurality of packages (such as SOJ packages) mounted thereto.
During the fabrication of IC packages, each IC package may be subjected to individual component-level testing, such as burn-in and electrical testing. An IC package that exhibits a desired level of performance during component level testing is generally referred to as a “known good device” or “known good die” while an IC package failing to meet minimum performance characteristics may be referred to as a “known bad device.” During the fabrication and assembly of multi-chip modules, an IC package may again be subjected to testing. Testing of a multi-chip module—module level testing—may include burn-in, electrical characterization and performance evaluation, as well as other desired electrical testing.
If a multi-chip module fails to exhibit minimum operating characteristics during module level testing, an IC package causing the failure—which may have previously been identified as a “known good device” during component level testing—must be removed from the multi-chip module and replaced. Also, it may be desirable to introduce a “known bad” IC package into a multi-chip module for module level testing in order to observe the electrical characteristics of the multi-chip module with the “known bad” IC package, or to observe the electrical characteristics of the “known bad” IC package at the module level. After module level testing is complete, the “known bad” IC package must be removed from the multi-chip module and replaced. Thus, although individual IC packages are typically tested at the component level, it is desirable to subject IC packages to further testing at the module level, as a “known good device” may fail at the module level and, further, because incorporation of a “known bad device” in a module may be useful in module level testing.
To test IC packages in a multi-chip module environment, module level testing is generally performed after the IC packages are assembled into—and permanently attached to—a multi-chip module carrier substrate. Thus, if an IC package must be removed from a multi-chip module after module level testing, the permanent electrical bonds between the external leads of the IC package and the contact pads on the multi-chip module carrier substrate must be severed. Severing the permanent electrical bonds—which typically comprise solder or conductive epoxy—may cause both heat-induced and mechanical damage to the multi-chip module substrate and conductors, to the external leads and electrical bonds of the IC packages remaining on the multi-chip module, and to other electrical components mounted on the multi-chip module.
To prevent heat-induced and mechanical damage resulting from severing of the permanent electrical bonds between the external leads of an IC package and a plurality of contact pads on a multi-chip module, IC packages may be non-permanently attached to a multi-chip module during module level testing. Use of non-permanent connections between the external leads of an IC package and a contact pad array allows for easy removal of the IC package after module level testing without any resulting damage from the severing of permanent electrical bonds. Devices for non-permanently attaching an IC package to a substrate, such as test sockets, clamps, and fixtures, are well known in the art.
Use of non-permanent electrical connections between the external leads of an IC package and a contact pad array on the multi-chip module can, however, itself cause problems during module level testing. Non-planarities in the multi-chip module carrier substrate, in the conductors forming a contact pad array, or in the IC package itself, may—in the absence of a permanent bonding agent—result in poor electrical contact between an external lead of the IC package and a corresponding contact pad on the multi-chip module. Similarly, for some types of IC packages such as the SOJ package, def
Brunelle Steven J.
Nguyen Phoung A.
Karlsen Ernest
Tang Minh N.
TraskBritt
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