Test mode switching system for LSI

Details Test mode switching system for LSI Test mode switching system for LSI

1990-01-03

1992-09-01

Smith, Jerry

Excavating

371 151, G06R 1100

Patent

active

051446278

ABSTRACT:
A test mode switching system includes a register for storing test signal data and for outputting the test signal data to a self testing circuit for checking whether or not the LSI operates correctly. A memory stores a test inhibiting signal and a test allowing signal received from a CPU through the control signal terminal of the LSI. The register is enabled to output test signals depending on the condition of the output of the memory whereby the LSI can operate either under a normal operation mode or under a test mode.

REFERENCES:
patent: 4546472 (1985-10-01), Volk et al.
patent: 4697140 (1987-09-01), Saito et al.
patent: 4742486 (1988-05-01), Takemae et al.
patent: 4837765 (1989-06-01), Suzuki
Patent Abstracts of Japan, vol. 9, No. 13 (P328) (1736) Jan. 19, 1985, * JP-A-59 160 778 (Nippon Denki KK.).

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