Test mode setting arrangement for use in microcomputer

Details Test mode setting arrangement for use in microcomputer Test mode setting arrangement for use in microcomputer

1991-11-29

1994-03-01

Harvey, Jack B.

Boots, shoes, and leggings

364579, 395425, 395725, 371 225, 371 226, G01N 2700

Patent

active

052914259

ABSTRACT:
A test mode setting arrangement provided in a microcomputer includes an internal memory, a plurality of pins and a central processing unit, the central processing unit being allowed to access the internal memory or an external memory depending on a logic level of a mode signal applied to the microcomputer, the arrangement basically features: a first unit for resetting the central processing unit in response to a reset control signal applied thereto, the reset control signal and the mode signal exhibiting essentially the same maximum voltage; a second unit for changing the output thereof in response to the logic level change of the mode signal, the second unit issuing an output which is applied to the central processing unit as a test mode initiating signal; and a third unit coupled to receive the mode signal and the output of the second unit, the third unit producing two signals which selects the access of the central processing unit to one of the internal and external memories.

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patent: 5086505 (1992-02-01), Goldberg et al.
patent: 5103167 (1992-04-01), Ohano et al.

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