Test mode latching scheme

Details Test mode latching scheme Test mode latching scheme

1996-12-23

1999-08-10

Chung, Phung M.

Excavating

371 2236, G11C 2900

Patent

active

059369736

ABSTRACT:
A novel synchronous latching scheme is disclosed for use in connection with an EPROM device having a limited number of pins for control signals. A negative edge-triggered d-type master-slave latch having a D-input, and a clock input is provided for generating a program/verify read mode signal. The D-input is coupled to a V.sub.pp /OE control terminal of the EPROM, while the clock input is coupled to a CE/PGM control terminal. During a program interval, while an enabled memory cell is being programmed, and the V.sub.pp control terminal is at a supervoltage, the latch is operable to capture the high level on such control terminal, and provide the high level as an output to define a verify read mode signal. During an immediately-following program verify read interval, the asserted verify mode signal is used to adjust the sense amplifier of the EPROM device so as to provide an increased read margin. During such verify program interval, the V.sub.pp /OE control terminal goes low to enable the outputs of the EPROM device. Such low signal is captured by the latch during the verify interval using the CE/PGM signal as a clock, such that the verify mode signal is driven low. With the verify mode signal in a logic low state, subsequent read operations of the EPROM chip occur as standard reads, since the sense amplifiers associated with the memory array of the EPROM device employ a standard reference signal, not the verify reference signal designed to add read margin.

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