Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-07-10
2004-08-31
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189050, C365S230060
Reexamination Certificate
active
06785162
ABSTRACT:
This application claims priority under 35 U.S.C. 119 from Italian Application No. RM2001A000556 filed Sep. 12, 2001, which application is incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to memory devices, and more particularly, to a test mode decoder in a flash memory device.
BACKGROUND
Electrically erasable and programmable read-only memory devices having arrays of what are known as flash cells, also called flash EEPROMs or flash memory devices, are found in a wide variety of electrical devices. A flash memory device is typically formed in an integrated circuit. A conventional flash cell, also called a floating gate transistor memory cell, is similar to a field effect transistor, having a channel region between a source and a drain in a substrate and a control gate over the channel region. In addition the flash cell has a floating gate between the control gate and the channel region. The floating gate is separated from the channel region by a layer of gate oxide, and an inter-poly dielectric layer separates the control gate from the floating gate. Both the control gate and the floating gate are formed of doped polysilicon. The floating gate is floating or electrically isolated. The flash memory device has a large number of flash cells in an array where the control gate of each flash cell is connected to a word line and the drain is connected to a bit line, the flash cells being arranged in a grid of word lines and bit lines.
A flash cell is programmed by applying approximately 10 volts to the control gate, between 5 and 7 volts to the drain, and grounding the source and the substrate to induce hot electron injection from the channel region to the floating gate through the gate oxide. The voltage at the control gate determines the amount of charge residing on the floating gate after programming. The charge affects current in the channel region by determining the voltage that must be applied to the control gate in order to allow the flash cell to conduct current between the source and the drain. This voltage is termed the threshold voltage of the flash cell, and is the physical form of the data stored in the flash cell. As the charge on the floating gate increases the threshold voltage increases.
One type of flash memory device includes an array of multi-bit or multi-state flash cells. Multi-state flash cells have the same structure as ordinary flash cells and are capable of storing multiple bits of data in a single cell. A multi-bit or multi-state flash cell has multiple distinct threshold voltage levels over a voltage range. Each distinct threshold voltage level corresponds to a set of data bits, with the number of bits representing the amount of data which can be stored in the multi-state flash cell.
Data is stored in conventional flash memory devices by programming flash cells that have been previously erased. A flash cell is erased by applying approximately −10 volts to the control gate, 5 volts to the source, grounding the substrate and allowing the drain to float. In an alternate method of erasure the control gate is grounded and 12 volts is applied to the source. The electrons in the floating gate are induced to pass through the gate oxide to the source by Fowler-Nordheim tunneling such that the charge in the floating gate is reduced and the threshold voltage of the flash cell is reduced. Flash cells in an array in a flash memory device are grouped into blocks, and the cells in each block are erased together.
A flash cell is read by applying approximately 5 volts to the control gate, approximately 1 volt to the drain, and grounding the source and the substrate. The flash cell is rendered conductive and current between the source and the drain is sensed to determine data stored in the flash cell. The current is converted to a voltage that is compared with one or more reference voltages in a sense amplifier to determine the state of the flash cell. The current drawn by a flash cell being read depends on the amount of charge stored in the floating gate.
A flash memory device is fabricated as an integrated circuit and then tested before being operated commercially by a user. Each flash memory device is slightly different from others of the same design because of the unique process conditions of its fabrication and other factors. As a result, each flash memory device has operating characteristics that are slightly different from the characteristics of other flash memory devices. For example, the flash cells of the flash memory device may be programmed at slightly lower control gate voltages than other flash cells.
Programmable control parameters have been used to control the operation of a flash memory device, and the control parameters can be programmed into data storage units after a flash memory device has been fabricated. The control parameters have been used to determine operating parameters for a flash memory device to compensate for its unique operating characteristics determined during fabrication, and the use of control parameters improves its performance. The control parameters are programmed in a test mode of operation following fabrication. The flash memory device is subject to a series of tests during the test mode, and the control parameters are programmed to set operating parameters such as reference voltage levels and the magnitude and duration of voltage pulses.
The control parameters can also be programmed to select operating modes and a configuration for the flash memory device. A wide variety of flash memory devices are used in electronic devices, and different flash memory devices have different configurations and different operating modes depending on the application. The control parameters make it possible to fabricate flash memory devices according to a single design, and then customize the configuration and operating modes of each individual flash memory device according to its application. Each flash memory device can be customized by programming its control parameters during the test mode.
A flash memory device is operated in the test mode in response to specific signals that are decoded by a test mode decoder circuit in the flash memory device. The purpose of the test mode decoder circuit is to start the test mode in response to the appropriate signals, and to prevent the flash memory device from entering the test mode if the appropriate signals are not present. The test mode decoder circuit is a safety device that reduces the likelihood that the control parameters will be changed by accident or mishap. An unwanted change in the control parameters can disable the flash memory device in its application.
The capacity of flash memory devices to store data is gradually being increased by reducing the size and increasing the number of flash cells in each integrated circuit. Other components, including the test mode decoder circuit, must also be reduced in size in order to improve the capacity of flash memory devices. There remains a need for a test mode decoder circuit that is smaller than conventional circuits.
SUMMARY OF THE INVENTION
The above mentioned and other deficiencies are addressed in the following detailed description. Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors to reduce the size of the decoder. The decoder may be fabricated with a flexible placement
D'Ambrosio Elio
Naso Giovanni
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