Test mode control logic system

Details Test mode control logic system Test mode control logic system

1978-10-31

1980-11-25

Smith, Jerry

Boots, shoes, and leggings

371 22, G06F 304, G06F 1122

Patent

active

042362083

ABSTRACT:
A logic control system is disclosed for verifying the operability of memory and non-memory data and control paths in both local and remote intersystem link (ISL) units electrically interconnecting a local and remote communication bus in a data processing system. The data processing system may include two or more communication busses each pair of which are electrically interconnected by twin ISL units. The control logic architecture accommodates the receipt of a test mode command from a CPU on a local bus to initiate a test mode operation wherein the memory and non-memory data and control paths of both the local and the remote ISL units are excerised while on-line, and binary coded information received from the local bus is passed through the ISL units, onto the remote bus, and returned to a local bus memory resource for verification. No remote bus resources are used or affected, and the remote ISL unit shall ignore any communications received from any other data processing unit on the remote bus. The remote ISL unit is effectively non-existent to other data processing units on the remote bus.

REFERENCES:
patent: 3480914 (1969-11-01), Schlaeppi
patent: 4041460 (1977-08-01), Wisdom et al.
patent: 4106091 (1978-08-01), Hepworth et al.

Affiliated with

Also associated with

Rating

Test mode control logic system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test mode control logic system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test mode control logic system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1133015