Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2002-09-24
2004-09-28
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C438S006000, C324S765010
Reexamination Certificate
active
06799133
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a test mode control circuit for reconfiguring a device pin of an integrated circuit chip to function as a test pin in a test mode and then revert to its device pin function in normal mode.
BACKGROUND OF THE INVENTION
Today, high resolution analog to digital converters (ADCs) are being assembled in smaller geometry, low pin count packages. Small outline packages, with as few as six pins, are good examples. This low pin count poses particular design issues for high resolution ADCs as there just are not enough pins to provide the functionality required. Traditionally ADCs have an analog input pin, dedicated reference inputs, separate power supplies—for both analog and digital circuitry—and a data interface.
All of this functionality has been merged into six pins. One pin is needed for the analog input, two pins are needed for the power supplies/references, and three pins are needed by the digital interface to allow standard connectivity to microprocessors and digital signal processors (DSPs). High resolution ADCs generally require some form on in-package trimming to achieve the precise component accuracy required and this requires data to be written to the part during a test mode.
AVDD positive power supply and reference
AGND negative power supply and reference
AIN analog inputsignal to be digitized
SCLK data interface: serial clock input
CSB data interface: framing signal and sample/convert input
DOUT data interface: output data
With this standard digital interface pin assignment it is not possible to write data to the integrated circuit. AIN is a very sensitive analog input so it is unwise to multiplex the test data through this pin. SCLK is the serial clock that controls the analog-to-digital conversion. CSB is a chip select signal. Because of the reduced number of pins this input already doubles up as the convert start (sample) signal and frame synchronization signal for the output data. DOUT is a dedicated output pin. It outputs conversion data when CSB is logic low and is high-impedance when CSB is logic high. The high impedance state is used when many ADCs are linked together to use a common clock and wire-ored data output.
Small form-factor, hand-held, battery powered equipment is pushing package technology to smaller geometries and lower pin counts. More products will have to sacrifice dedicated test mode pins in order to meet this challenge. Another feature that is becoming more common in new product design is the ability to design a general purpose circuit that can be programmed, after wafer fabrication, into a family of derivative parts. Traditionally this was achieved by a separate development and/or metal masks. As process technology shrinks and wafer sizes increase the number of good die from a wafer lot can exceed the lifetime sales of a particular metal mask derivative. Products such as ADCs, switches, and muxes do not have dedicated test modes or test access so a workaround is needed to address the trimming and configuration (derivative) issue.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an improved test mode control circuit for reconfiguring a device pin of an integrated circuit chip which is initially in a test mode for trimming/reconfiguring an associated circuit.
It is a further object of this invention to provide such an improved test mode control circuit for reconfiguring a device pin of an integrated circuit chip which employs a normal device pin as a test pin in the test mode and then returns it to its device pin function when the test mode trimming/reconfiguring is finished.
It is a further object of this invention to provide such an improved test mode control circuit for reconfiguring a device pin of an integrated circuit chip in which the device pin is reconfigured from test pin back to device pin functionality in response to the logic state of a separate input pin.
It is a further object of this invention to provide such an improved test mode control circuit for reconfiguring a device pin of an integrated circuit chip which enables test access for low pin count integrated circuit chip packages.
It is a further object of this invention to provide such an improved test mode control circuit for reconfiguring a device pin of an integrated circuit chip which enables in-package testing for more accurate integrated circuits such as analog to digital converters.
It is a further object of this invention to provide such an improved test mode control circuit for reconfiguring a device pin of an integrated circuit chip which enables easy reconfiguring of generic designs into a variety of standard parts.
The invention results from the realization that test access to even low pin count integrated circuit chips for trimming and reconfiguring the on board integrated circuits can be achieved by reconfiguring a device pin to function as a test pin under control of the logic state of a second pin coupled with the use of an on-chip programmable array which is preset during manufacturing to the test mode and which can be used to permanently trim and/or reconfigure components after which it can be reset to the normal mode to reestablish the normal function of the device pin.
This invention features a test mode control circuit for reconfiguring a device pin of an integrated circuit chip which is initially configured in a test mode. An input register applies trim/configuring data to one or more components on an integrated circuit chip. There is a device pin and an output register for receiving output data from an integrated circuit on the integrated circuit chip which integrated circuit has had one or more of its elements trimmed/reconfigured. An I/O logic circuit controls the device pin to operate as a test pin to selectively deliver the trim/configuring data to the input register and receive output data from the output register. A programmable array includes a plurality of logic state elements for permanently mapping a selected set of the trim/configuring data from the input register. The programmable array includes a test bit. A switching system applies the trim/configuring data to the one or more components on the integrated circuit when the test bit is in a first, test mode and applies the permanently mapped trim/configuring data to the components in a second normal mode.
In a preferred embodiment, the switching system may include a multiplexor. A logic state element may includes fuses, anti-fuses, EEPROMs, or similar devices. The test bit may be initially in the first, test mode. The I/O logic circuit may respond to the logic state of a second pin and the test bit to enable the device pin to selectively output or input data. The I/O logic circuit is responsive to the test bit being in the test mode and the second pin being in one of first and second states to configure the device pin to provide input and output data, respectively, and to the test bit being in the normal mode and the second pin being in one of first and second states to configure the device pin to provide high impedance and output data, respectively.
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McIntosh Colin S.
Price Colin C.
Analog Devices Inc.
Hoff Marc S.
Iandiorio & Teska
Raymond Edward
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