Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-08-07
2002-12-03
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185020, C365S185190
Reexamination Certificate
active
06490198
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test method of measuring a disturbance value and a disturbance margin that are caused when a program disturbance stress is applied to a semiconductor non-volatile memory comprising a plurality of memory cells each having a gate, a floating gate, a drain, and a source.
2. Description of the Prior Art
A flash memory is one of such semiconductor non-volatile memories having a floating gate. A structural example of a semiconductor non-volatile memory is shown in FIG.
15
.
FIG. 15
shows a simplified cross-sectional view of the semiconductor non-volatile memory. This memory cell has a gate
1
having a control terminal
11
, a floating gate
2
, a drain
3
having a drain terminal
13
, and a source
4
having a source terminal
14
. A tunnel oxide layer
6
is formed between a substrate
5
and the floating gate
2
.
A memory cell
21
shown in
FIG. 15
takes either of two statuses, a programmed status (“
1
”) or an erased status (“
0
”) depending on an amount of charge stored in the floating gate
2
. For example, when a channel formed between the drain
3
and the source
4
becomes non-conductive, the status of the memory cell is defined as “
0
”, and as “
1
” when the channel becomes conductive. In this way, the memory cell can hold and provide two-level data depending on the amount of charge stored in the floating gate
2
.
By applying, for example, a positive voltage to the control terminal
11
, and a negative voltage to the substrate
5
, the drain terminal
13
, and the source terminal
14
, electrons are injected from the channel formed between the drain
3
and the source
4
into the floating gate
2
by a phenomenon called Fowler-Nordheim tunnel effect (hereinafter referred to as FN tunnel effect). Thus, the data of the memory cell is set to “
0
”. Under this condition, the negative charge stored in the floating gate
2
behaves like a barrier and prevents a current from flowing between the drain
3
and the source
4
even if a positive voltage is applied to the control terminal
11
.
On the other hand, by applying, for example, a negative voltage to the control terminal
11
and a ground level to the substrate
5
, and also by applying a positive voltage to the drain terminal
13
, the negative charge that has been stored in the floating gate
2
is pulled out to the drain. Thus, the data of the memory cell is set to “
1
”. Under this condition, applying a positive voltage to the control terminal
11
allows a current to flow between the drain
3
and the source
4
.
A memory cell array is composed of a plurality of such memory cells as described before.
FIG. 16
shows an example of memory cell array circuit. A memory cell array
31
has six memory cells,
21
a
to
21
f
(hereinafter, these memory cells in
FIG. 16
are collectively referred to as memory cell
21
). The control terminal
11
of each memory cell is connected to a word line
32
. Furthermore, the drain terminal
13
of one particular memory cell and the source terminal
14
of an adjacent memory cell are connected to a bit line
33
. The memory cell array
31
is provided with seven bit lines,
33
a
to
33
g
(hereinafter, these bit lines in
FIG. 16
are collectively referred to as bit line
33
).
Before writing data to the memory cell array
31
, memory cells should be erased by an injection of an excessive amount of negative charge into the floating gate
2
thereof. Then, for example, as shown in
FIG. 16
, a negative voltage −Vg is applied to the word line
32
to which each control terminal
11
of the memory cell
21
is connected. For example, if data “
0
” is written to the memory cell
21
d
, the bit line
33
e
connected to a drain terminal
13
f
thereof should be left floating (F), (hereinafter, all the drain terminals that are left floating are referred to as
13
f
). When, for example, writing data “
1
” to the memory cell
21
b
, the positive voltage +Vd is applied to the bit line
33
c
to which the drain terminal
13
thereof is connected.
When writing data “
0
”, the negative charge does not move from a floating gate
2
f
(hereinafter, the floating gate storing the negative charge is referred to as
2
f
) to the drain because the drain terminal
13
f
is left floating, and therefore a sufficiently high electric field to initiate the FN tunnel effect will not be generated in the tunnel oxide layer
6
. On the other hand, when writing data “
1
”, the negative charge moves from the floating gate
2
to the drain because the positive voltage +Vd is applied to the drain terminal
13
generating a sufficiently high electric field to initiate the FN tunnel effect in the tunnel oxide layer
6
. In this way, data “
1
” is written to the memory cell.
Individual memory cells that altogether constitute a memory cell array are not uniform in properties because of manufacturing variations or the like. When writing to memory cells (programming), as described before, the negative voltage −Vg is applied as a stress voltage through a word line to the control terminal of the memory cell that is supposed to be written to “
0
”. Considering these factors, if a plurality of memory cells sharing an identical word line have a fairly large amount of variations in properties, some memory cells may switch from “
0
” to “
1
” when the negative charge stored in the floating gate thereof moves to the drain initiated by the FN tunnel effect despite that the bit line thereof is left floating. In this way, the stress voltage may cause a threshold voltage to decline.
It is, therefore, extremely important to measure the amount of disturbance received by each memory cell that altogether constitutes a memory cell array. In constructing a test program algorithm, it is also important to measure a disturbance margin which is an indication of margin between the algorithm of the test program and the actual memory cells to be tested. These values can be also utilized as criteria during an outgoing inspection of products.
Measuring the program disturbance value and the disturbance margin that indicate an amount of disturbance when the memory cells are programmed, is an intrinsically necessary test regardless of types of flash memories. Specifically, if the polarity of writing voltage or the like is optimally adjusted, this test method can be employed for testing such flash memories as NOR, NAND, DINOR, virtual-ground NOR types, and the like regardless of types. Mentioned hereunder are examples of the conventional test methods for evaluating the amount of program disturbance on memory cells.
Test Method 1
An extremely common evaluation method includes steps to apply to erased memory cells, a program disturbance stress that is equivalent to the one prescribed by specifications, then to read each memory cell, and to evaluate the result to see if the memory cells still maintain the erased status.
Test Method 2
Another program disturbance stress test includes steps to apply to the erased memory cells, a program disturbance stress that is equivalent to the one prescribed by specifications or the like, then to evaluate whether or not the resultant threshold levels have exceeded the specified level or the like.
Test Method 3
In order to conduct a more accurate test for the program disturbance margin, another test includes a first procedure to measure the time or the number of program pulse steps required for completing programming all the memory cells that undergo the programming operation simultaneously. In a second procedure, among identical memory cells, the time or the number of pulse steps required for the first memory cell to shift from the erased level to the programmed level after being stressed under the program disturbance will be measured. The results in terms of the time or the number of steps obtained through the above two procedures will be compared for evaluation.
However, the above-mentioned test methods have the following shortcomings. a Test method 1 is only effective for judging if some memory cell
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
Zarabian A.
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