Test methods and structures for semiconductor integrated circuit

Details Test methods and structures for semiconductor integrated circuit Test methods and structures for semiconductor integrated circuit

1980-11-24

1982-08-31

Karlsen, Ernest F.

Electricity: measuring and testing

Conductor identification or location

Inaccessible

324 65R, 324158R, 430 30, G01R 2714, G01R 3100

Patent

active

043474799

ABSTRACT:
Test methods and structures are provided for electrically monitoring the image size tolerance (.DELTA.W) during a critical photolithographic step in the processing of a semiconductor wafer. The test structure includes two symmetrical resistor bridges combined into a single structure exhibiting a specific topology and having specific nominal parameters of length and width. The structure further includes contact regions and contact voltages are respectively measured across the first and second bridges. The size tolerance is determined from the voltages. Therefore, the factor .DELTA.W is directly determined by means of simple electrical measurements and, therefore, a data base is immediately provided with respect to the wafer in which the structure exists. Also, this invention relates to a method for monitoring the electrical tolerance (.DELTA.A) where images are superimposed, which uses the preceding calculation.

REFERENCES:
patent: 3922707 (1975-11-01), Freed et al.
patent: 3974443 (1976-08-01), Thomas
T. H. Baker et al., "Dumbbell-Type Resistance Testing Structure", IBM Technical Disclosure Bulletin, vol. 14, No. 12, May 1972, p. 3707.
M. G. Buehler et al., "Bridge and Van der Pauw Sheet Resistors for Characterizing the Line Width of Conducting Layers", Journal of the Electrochemical Society, vol. 125, No. 4, Apr. 1978, pp. 650-654.
D. S. Perloff, "A Four-Point Electrical Measurement Technique for Characterizing Mask Superposition Errors on Semiconductor Wafers", IEEE Journal of Solid State Circuits, vol. SC-13, No. 4, Aug. 1978, pp. 436-444.

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