Test methodology for exceeding tester pin count for an asic devi

Details Test methodology for exceeding tester pin count for an asic devi Test methodology for exceeding tester pin count for an asic devi

1996-04-04

1998-01-27

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057128588

ABSTRACT:
An electronic testing system can test an electronic device which has more signal pins or pads (i.e., contacts) than the maximum number of tester probes. The testing system connects the contacts to the tester such that groups of contacts share individual tester signal lines. The testing system uses special selector logic on the device to be tested to determine which particular contacts of the groups are "currently output active", or capable of transmitting data. At each step in the testing procedure, the system can vary the sets of contacts which are chosen to be currently output active, thereby resulting in a high percentage of the possible states of the device being tested.

REFERENCES:
patent: 5068603 (1991-11-01), Mahoney

Affiliated with

Also associated with

Rating

Test methodology for exceeding tester pin count for an asic devi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test methodology for exceeding tester pin count for an asic devi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test methodology for exceeding tester pin count for an asic devi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-347800