Test/master/slave triple latch flip-flop

Details Test/master/slave triple latch flip-flop Test/master/slave triple latch flip-flop

1985-11-04

1987-09-29

Miller, Stanley D.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular input circuit

377 77, 3072721, 328104, 328105, G11C 1900

Patent

active

046972790

ABSTRACT:
A shift register stage (20) for LSI and VLSI circuits is disclosed and includes a first latching circuit (21) responsive to a data input and for providing a first data output; control circuitry (23) responsive to the first data output and to a parallel data input for providing as a controlled data output a replica of the first data output or a replica of the parallel data input as a function of a control signal; a second latching circuit (25) responsive to the controlled data output and for providing a second data output; and a third latching circuit (27) responsive to the second data output and for providing a third data output. Also disclosed is a shift register (30) for LSI and VLSI circuits which advantageously utilizes the foregoing shift register stage of the invention and which provides for AC or delay testing of an integrated circuit which includes two of such shift registers (30, 60) and a logic network (50) interposed therebetween.

REFERENCES:
patent: 4390987 (1983-06-01), Best
patent: 4495628 (1985-01-01), Zasio
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4580137 (1986-04-01), Fiedler et al.

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