Test key layout for detecting via-open failure

Details Test key layout for detecting via-open failure Test key layout for detecting via-open failure

2001-04-26

2003-04-29

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06556035

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a test key layout. More particularly, the present invention relates to a test key layout for detecting via-open failure.
2. Description of Related Art
To increase product yield in mass production, most semiconductor manufacturers specifically design various types of test keys for finding defects in various component parts due to unexpected processing errors. Once a defective component is found, causes of failure can be investigated and later rectified.
In recent years, a number of methods for finding inter-metallic via-open failure have been developed. One method, for example, uses an electron beam as an incident source for failure detection. Most inspection methods include bombarding a test specimen with an electron beam and collecting the secondary electrons (SE) thus produced. Topographic information of the test specimen is obtained by gauging the secondary electrons.
Via-open failure detection using an electron beam is very much simplified if the test keys are laid out as a layer of metal over a substrate. In addition, the metallic layer is covered by a dielectric layer having a plurality of vias therein with each via having a metallic bonding pad thereon. When a beam of electrons shines on the test keys, vias in the closed state as well as vias in the open state underneath the metallic bonding pads are activated to produce secondary electrons. However, the vias in the closed state generate more secondary electrons than the vias in the open state. After photographic processing, bright spots appear in the closed vias while dark or fuzzy sports will appear in the open vias. Such a strong photographic contrast between open vias and closed vias serves to pinpoint the exact location of via-open failures in a test specimen.
Due to the miniaturization of semiconductor transistors in a silicon chip, most integrated circuit chips use two or more metallic layers for interconnection. In particular, four or five metallic layers are often used in multi-functional electronic products such as a microprocessor. As the number of interconnects increases, the finding of interconnect failures is increasingly critical, especially via-open failures.
FIG. 1
is a schematic cross-sectional view showing a conventional test key layout for finding via-open failures in a multi-layered circuit.
As shown in
FIG. 1
, a substrate
100
having three metallic layers
101
,
102
and
103
thereon to serve as interconnects for various devices is formed. The metallic layer
101
represents a first metallic layer (M
1
), the metallic layer
102
represents a second metallic layer (M
2
) and the metallic layer
103
represents a third metallic layer (M
3
). A plurality of first vias (V
1
)
104
is formed between the first metallic layer
101
and the second metallic layer
102
. A plurality of second vias (V
2
)
105
is formed between the second metallic layer
102
and the third metallic layer
103
. A second via
106
between the second metallic layer
102
and the third metallic layer
103
is in an open state.
In general, the electron beam method for finding via-open failures in multi-layered interconnects is carried out in stages according to the formation sequence of inter-metallic vias. However, via-open failure detection is often not very accurate because in a conventional test key layout, various metallic layers are linked by vias. Hence, when an electron beam impinges upon an open-via such as
106
, electrons are able to pass from the third metallic layer
103
down the closed-via
105
to reach the metallic layer
102
underneath. In fact, the flow of electrons in this manner is identical to the passage of electrons through closed-via
105
. Therefore, for the second vias
105
and
106
underneath the third metallic layer
103
, difference in activated secondary electrons for electron beam falling on the open-via
106
and the closed-via
105
is minor. Since contrast between the two vias
105
and
106
after photographic processing is small, indeterminate results are often obtained.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a test-key layout for finding via-open failures such that photographic contrast is enhanced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a test-key layout for finding via-open failures through an electron beam. The layout includes two types of test-key layout. One test-key layout is designed for testing the vias underneath even-numbered metallic layers. The other test-key layout is designed for testing the vias underneath odd-numbered metallic layers. Every pair of metallic layers is assigned into a group such that there is no interconnect for linking between the groups and the upper metallic layer in each group has an open circuit design. Furthermore, it does not matter if the metallic interconnect layer belongs to an odd or an even layer; a via-open failure analysis of the vias between metallic layers is conducted using the aforementioned two test-key layouts.
This invention provides a test-key layout for finding via-open failure. The test-key layout design includes assigning two metallic layers to a group with no linkage between each pair and forging an open-circuit design for the upper metallic layer in each group so that via-open failures are more prominent. Ultimately, via-open failures are more easily found and rectified, resulting in a higher product yield.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5262719 (1993-11-01), Magdo
patent: 5949240 (1999-09-01), Yeh
patent: 6133055 (2000-10-01), Yeh
patent: 6191602 (2002-02-01), Huang Lu et al.
patent: 6452412 (2002-09-01), Jarvis et al.

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