Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-05-22
2002-09-17
Schuberg, Darren (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S760000, C361S082000, C257S700000, C257S737000, C257S686000, C439S066000, C439S068000, C324S754090, C324S755090, C324S758010
Reexamination Certificate
active
06452807
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to ball grid array (“BGA”) packages and methods of testing or otherwise evaluating BGA packages. In particular, the present invention relates to test interposers that may be disposed between a BGA semiconductor device and a carrier substrate with which the BGA semiconductor device is in electrical communication. The present invention also includes BGA packages that include the interposer sandwiched between a BGA semiconductor device and a carrier substrate. The present invention also relates to methods of testing or otherwise evaluating BGA packages by employing the interposer of the invention.
2. Background of the Related Art
Ball grid array (“BGA”) packages typically include a semiconductor die that has bond pads disposed over an active surface thereof, rather than merely proximate a periphery thereof. Thus, the bond pads of BGA semiconductor dice may be disposed across the active surfaces of the BGA semiconductor dice at an increased density relative to the bond pads disposed on conventional semiconductor dice with peripherally located bond pads. Therefore, BGA semiconductor dice may have smaller dimensions or an increased number of bond pads relative to the dimensions or number of bond pads of conventional semiconductor dice.
BGA packages typically include a carrier substrate to which the BGA semiconductor dice are flip-chip bonded, TAB bonded, or otherwise invertedly secured. Thus, the footprint of the terminals of the BGA carrier substrate corresponds substantially to the footprint of bond pads on an inverted BGA semiconductor die. As the use of BGA packages eliminates conventionally employed wire bonds that typically extend past the periphery of a semiconductor die to establish an electrical connection between the semiconductor die and a carrier substrate, the circuit density of the carrier substrate may be increased.
In order to test or otherwise evaluate the characteristics of the electrical signals transmitted to and from BGA packages, some manufacturers have employed specially designed test substrates in place of the carrier substrate. These test substrates may include test pads that extend from the circuitry of the test substrate. The use of such test substrates is, however, somewhat undesirable in that the circuitry of the test substrate does not accurately represent the circuitry of a corresponding carrier substrate to be employed in production of the BGA package. For example, the test substrate and production carrier substrate may have different circuit patterns, different circuit lengths, and different circuit densities. Thus, the circuits of the test substrate could consume more “real estate” on the test substrate than the circuits of a production carrier substrate, the circuits of the test substrate may not be optimally electrically routed for production, or the electrical characteristics of the test substrate may otherwise differ substantially from the electrical characteristics of a corresponding production carrier substrate.
Another approach to testing BGA packages involves the use of an interposer with test posts extending upwardly from the periphery of the interposer around the BGA semiconductor die. As each of the upwardly extending test posts of such an interposer would have to be electrically optimized, the electrical characteristics of a BGA package including such an interposer would not accurately represent the electrical characteristics of a similar BGA package without the interposer. Moreover, these upwardly extending test posts may act as antennas and may, therefore, interfere with the electrical properties of the BGA package or of any proximate circuit traces or other electrical components. Test interposers that include such upwardly extending test posts are also undesirable from the standpoint that the test posts may increase the overall height of BGA packages including the interposer and may, therefore, decrease the usefulness of the test interposer in production-level BGA packages (i.e., BGA packages with this type of interposer may not be salable).
Accordingly, there is a need for an interposer that may be employed to test or evaluate the electrical characteristics of signals transmitted to and from a BGA semiconductor die, that may be incorporated into a salable BGA package, and that will not interfere substantially with the electrical characteristics of the BGA package or any proximate electrical componentry.
BRIEF SUMMARY OF THE INVENTION
The BGA package test interposer of the present invention includes a substantially planar, electrically non-conductive structure with electrically conductive vias extending through a central region thereof; electrically conductive traces extending from each of the electrically conductive vias, continuously supported by the planar structure, toward a periphery, or peripheral region, of the substantially planar structure; and a test pad in electrical communication with each of the electrically conductive traces. Due to its small size, the interposer is also useful in chip-scale packages (“CSPs”).
Each of the electrically conductive vias of the test interposer is preferably positioned upon the substantially planar structure to correspond to a bond pad of a BGA semiconductor die to be disposed adjacent a first surface of the substantially planar structure and to an electrical terminal of a carrier substrate to be disposed adjacent a second surface of the planar structure. Thus, in an assembly including a BGA semiconductor die, the test interposer, and a carrier substrate, the test interposer may be flip-chip bonded, tape-automated bonded (“TAB”), or otherwise electrically connected, as known in the art, between the BGA semiconductor die and the carrier substrate.
The test pads of the test interposer may be disposed upon either or both surfaces of the planar structure. As a BGA semiconductor die may include up to one hundred or more bond pads, the test pads may be disposed proximate the periphery (i.e., on the peripheral region) of the planar structure in a staggered arrangement or in more than one row. Of course, the number of test pads on the test interposer may differ from the number of bond pads on the BGA semiconductor die since it may be desirable to evaluate signals transmitted through selected ones of the bond pads rather than signals transmitted through all of the bond pads.
As the test interposer of the present invention includes test pads disposed proximate the periphery thereof that may be insulated from substantially interfering with or deteriorating electrical signals, the interposer may be assembled with and incorporated into a production-level BGA package. Due to its relatively small size, the test interposer of the present invention may also be assembled with a BGA semiconductor die and attached to a carrier substrate without substantially increasing the amount of “real estate” consumed on the carrier substrate relative to the surface area consumed by the BGA semiconductor die alone and without significantly interfering with signals transmitted through the BGA semiconductor die or through the carrier substrate. Moreover, carrier substrates with electrically optimized circuit patterns may be employed in BGA package assemblies that include only a BGA semiconductor die and the carrier substrate, as well as in BGA package assemblies according to the present invention that also include a test interposer.
The present invention also includes a method of designing a test interposer, including configuring the substantially planar structure, the electrically conductive vias, the electrically conductive traces, and the test pads. The substantially planar structure has an outer periphery, which is also referred to as a peripheral region of the substantially planar structure, that is located outside of an outer periphery of a BGA semiconductor die to be assembled therewith. Thus, a peripheral portion of the substantially planar structure remains exposed after alignment and assembly of the substantially planar structure wit
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