Test interface for an MOS technology integrated circuit

Details Test interface for an MOS technology integrated circuit Test interface for an MOS technology integrated circuit

1986-10-10

1988-08-16

Smith, Jerry

Excavating

324 73R, G01R 3128

Patent

active

047649240

ABSTRACT:
This interface enables the integrated circuit with which it is associated to be placed in a test configuration by applying to its test input terminal (2) a voltage higher than the power supply voltage (V.sub.cc) of the circuitry. In the rest state, the interface then supplies a low logic level to its output terminal (5). If the test command voltage is applied, this level changes state.
The interface comprises, in particular, two transistors (M.sub.1, M.sub.2) of opposite types of conductivity which are fed by a constant current source (10, M.sub.5, M.sub.6). The interface switches over when the input transistor (M.sub.1) is put into the conducting state by the test command voltage so as to divert a fraction of the current flowing in the second transistor (M.sub.2).
The input terminal (2) can at the same time be a functional input terminal of the integrated circuit.

REFERENCES:
patent: 4229670 (1980-10-01), Thommen
patent: 4336495 (1982-06-01), Hapke
patent: 4398146 (1983-08-01), Draheim
patent: 4658156 (1987-04-01), Hashimoto

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