Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-11-15
2004-09-21
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S761010, C324S1540PB
Reexamination Certificate
active
06794887
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates a test head including a displaceable switch element.
A semiconductor integrated circuit die has an array of contact pads distributed in a predetermined pattern over a major surface of the die.
A conventional general-purpose semiconductor integrated circuit tester includes a test head and a wafer prober or device handler for positioning a device under test (DUT) at a test location for testing. For convenience, in the following description it will be assumed that the test head is in the so-called DUT down orientation in which the test head is oriented to engage a DUT whose major surface is presented upwards. The test head includes a support frame, a docking plate attached to the support frame at the bottom of the test head, and pin cards mounted in the support frame and each having multiple contact pins projecting downwards beyond the docking plate. The contact pins are distributed over a much greater area than the area of the major surface of the DUT. A load board is attached to the docking plate and has on one side (the test-head side) an array of pads that are engaged by the contact pins of the test head and on its opposite side (the DUT side) an array of pins for engaging the contact pads of the DUT. The load board includes conductors that connect the contact pads at the test-head side of the load board to the corresponding pins at the DUT side of the load board. The load board thus serves as an interface between the test head and the DUT.
The load board must be manufactured with a high degree of precision to ensure that all the contact pads will be and remain in the correct positions, within the applicable tolerances, over the intended useful life of the load board.
In addition to the conductors that connect the contact pads at the test-head side of the load board to the corresponding pins at the DUT side of the load board, the load board also includes any special circuits that are not contained in the general purpose tester but may be required in order to allow the general purpose tester to analyze a particular DUT. These circuits are often complex and they may be custom manufactured for use in the load board.
Each load board is designed for use with a DUT having a particular pattern of contact pads. A different load board may be required for each pattern of contact pads; and different load boards may even be required for different devices having the same pattern of contact pads. Accordingly, the operator of a testing facility may require a large number of load boards.
The stringent requirements regarding the physical structure of the load board, and the design, manufacture and support of the special circuits, result in the load board being very expensive to manufacture. Accordingly, it is desirable that the operator of a testing facility be able to use the load board designed for a particular device so long as there is demand for that device.
The contact pins of the test head are conventionally implemented using so-called pogo pins. A pogo pin includes a socket that is firmly secured in a support member, a barrel that is press fit into the socket, a plunger that is a sliding fit inside the barrel, and a spring inside the barrel urging the plunger toward a projecting position. The load board is positioned so that the tips of the plungers are in contact with the pads on the load board and the load board is then displaced towards the test head and secured to the docking plate, establishing electrically conductive pressure contact between the tip of each plunger and the respective contact pad.
Referring to
FIG. 1A
, the pin card that is used in one known form of tester has pogo pins positioned to engage contact pads arranged in two rows of nine pads. In each row, signal I/O pads, which are engaged by signal I/O pins of the pin card, alternate with ground pads, which are engaged by ground pins of the pin card. In this known form of tester, each pin card is able to support eight tester channels. The pin card may also include auxiliary pogo pins that engage auxiliary contact pads.
It has been proposed that in a new design of tester the pin card should have an inner row of eleven ground pins that are positioned to engage an inner row of eleven ground pads, and two outer rows of signal I/O pins that are positioned to engage respective outer rows of eight signal I/O pads, as shown in FIG.
1
B. The pin card may also include auxiliary pogo pins that engage auxiliary contact pads. A pin card in accordance with this proposal would be able to support sixteen tester channels.
The new design of tester has certain advantages with respect to the known form of tester, but it will be appreciated that the pin cards for the new design are not compatible with a legacy load board, i.e. a load board designed for use with the earlier tester, because the pin card does not ground alternate pins in the two outer rows of contact pads.
If a tester of the new design could be rendered compatible with a legacy load board, a testing facility equipped with a tester of the known form could upgrade to a tester of the new design without replacing its legacy load boards. Further, the facility could upgrade its capacity by sharing load boards between the tester of the known form and the tester of the new design.
SUMMARY OF THE INVENTION
In accordance with a first aspect of the invention there is provided a test head for a semiconductor integrated circuit tester, comprising a plurality of contact pins connected to tester channels of the tester, each contact pin having a free end for engaging a load board, and a conductive switch element displaceable between a first position, in which the switch element is electrically isolated from one or more contact pins, and a second position, in which the switch element is in electrically conductive contact with one or more contact pins.
In accordance with a second aspect of the invention there is provided a test head for a semiconductor integrated circuit tester, comprising a support frame, and a plurality of pin cards mounted in the support frame, each pin card including a plurality of contact pins connected to tester channels of the tester, each contact pin having a free end for engaging a load board, and a conductive switch element displaceable between a first position, in which the switch element is electrically isolated from one or more contact pins, and a second position, in which the switch element is in electrically conductive contact with one or more contact pins.
In accordance with a third aspect of the invention there is provided a pin card for mounting in a test head of a semiconductor integrated circuit tester to implement test channels of the tester, the pin card including a plurality of contact pins connected to terminals of respective test channels, each contact pin having a free end for engaging a load board, and a conductive switch element displaceable between a first position, in which the switch element is electrically isolated from one or more contact pins, and a second position, in which the switch element is in electrically conductive contact with one or more contact pins.
In accordance with a fourth aspect of the invention there is provided an assembly for attachment to a pin card of a semiconductor integrated circuit tester, comprising a pogo block, at least two pogo pins mounted in the pogo block, a conductive switch element mounted in the pogo block and displaceable between a first position, in which the switch element is electrically isolated from one or more pogo pins, and a second position, in which the switch element is in electrically conductive contact with one or more pogo pins.
REFERENCES:
patent: 4465972 (1984-08-01), Sokolich
patent: 5491427 (1996-02-01), Ueno et al.
Ellis Travis S.
Nelson Edward W.
Wohlfarth Paul D.
Credence Systems Corporation
Nguyen Vinh P.
Smith-Hill John
Smith-Hill and Bedell
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