Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-04-27
2002-10-01
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06459286
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the testing of semiconductor chips, particularly chip-sized packages (CSP). More particularly, the invention relates to a test head assembly which obviates the requirement of contacting a device-under-test (DUT) by way of pogo pins or other conventional devices.
BACKGROUND OF THE INVENTION
The testing of semiconductor chips is well known. Some conventional testing apparatus for semiconductor devices, such as CSPs, provide for an electrical contact between the device and a printed circuit board (PCB). The electrical contact is generally made through spring-loaded test probes or through pins extending through an intermediate section of a carrier. An example of spring-loaded test probes may be found in U.S. Pat. No. 5,823,818 (Bell et al.). Examples of the use of contact test pins may be found in U.S. Pat. No. 4,764,925 (Grimes et al.) and U.S. Pat. No. 5,875,198 (Satoh).
One potential deficiency in utilizing spring-loaded test probes, also known as pogo pins, or stationary pins, is the difficulty in properly attaching them to the DUTs. With the increasingly smaller device sizes, the electrical contacts are getting closer together, making the manufacture of the test device itself, with pogo pins or stationary pins, and the subsequent testing of the contacts with such a device even more difficult.
SUMMARY OF THE INVENTION
The present invention provides an apparatus for testing semiconductor devices including a base, an intermediate silicon contact structure supported by the base and having a plurality of electrical contacts for mating with the contacts of a DUT and which supplies signals between the DUT and a testing apparatus, and a fixing structure. The fixing structure holds the intermediate silicon contact structure to the base. The fixing structure has an opening through which a DUT may pass and be connected with the plurality of electrical contacts of the intermediate structure.
The present invention also provides a system for testing semiconductor devices. The system has a testing apparatus, which includes a base having at least one cavity with an opening extending from a cavity surface to a bottom surface of the base, an intermediate silicon contact structure supported by the base within one of the cavities and having a plurality of electrical contacts adapted to provide an electrical connection between the printed circuit board and a DUT, and a fixing structure which holds the intermediate structure to the base. The fixing structure has an opening through which a DUT may pass and be connected with the plurality of electrical contacts of the intermediate structure. The system further includes a printed circuit board positionable on the cavity surface which is electrically connected with the intermediate structure and with a testing apparatus, and a pick and place device for moving a DUT into electrical connection with the intermediate structure.
The present invention also provides a method for testing a semiconductor device. The method includes the steps of moving a semiconductor device into a semiconductor test apparatus, electrically connecting the semiconductor device to a testing apparatus through the intermediate silicon contact structure, and testing the semiconductor device with the testing apparatus.
These and other features and advantages of the invention will be more clearly understood from the following detailed description of the invention which is provided in connection with the accompanying drawings.
REFERENCES:
patent: 4764925 (1988-08-01), Grimes et al.
patent: 5640762 (1997-06-01), Farnworth et al.
patent: 5713744 (1998-02-01), Laub
patent: 5716218 (1998-02-01), Farnworth et al.
patent: 5730620 (1998-03-01), Chan et al.
patent: 5742481 (1998-04-01), Murphy et al.
patent: 5823818 (1998-10-01), Bell et al.
patent: 5847293 (1998-12-01), Elmer
patent: 5875198 (1999-02-01), Satoh
patent: 5878485 (1999-03-01), Wood et al.
patent: 6307394 (2001-10-01), Farnworth et al.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Le N.
LeRoux Etienne P
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