Test generator system for controllably inducing power pin latch-

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals

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371 223, 371 225, 348126, 382149, 324763, 2503581, G06F 7556

Patent

active

055415474

ABSTRACT:
A latch-up pulse generator system includes a latch-up pulse generator coupled to first and second power supplies, for outputting JEDEC-standardized first and second output pulse trains. The generator includes a master clock, digital frequency dividers, and digitally controlled delay circuitry for outputting the two pulse trains. The first pulse train is a square-wave signal with a repetition rate of about two seconds. The second pulse train has a pulse width that is digitally controllable between about 0.2 .mu.s and 5 .mu.s. The delay between the fall-time of the second pulse train and the fall-time of the first pulse train is variably controlled between about 1 .mu.s and one second in 1 .mu.s steps. The amplitude and current output of each pulse train may range from 0 to perhaps 15 VDC at a current level of about 5 A. For power pin latch-up testing, the two pulse trains are combined to produce a composite pulse train. Signal and/or power pins of a CMOS device under test may be analyzed. Digital control permits a user to halt latch-up at any point in the latch-up phenomenon for purposes of observation, analysis and recordation. Preferably a generic emission microscope is used to observe the device under test.

REFERENCES:
patent: 4532534 (1985-07-01), Ford et al.
patent: 4633283 (1986-12-01), Avery
patent: 4672407 (1987-06-01), Nakagawa et al.
patent: 4870530 (1989-09-01), Hurst et al.
patent: 5170239 (1992-12-01), Hagino
patent: 5326994 (1994-07-01), Giebel et al.
patent: 5391898 (1995-02-01), Hagino

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