Test-facilitating circuit and testing method

Details Test-facilitating circuit and testing method Test-facilitating circuit and testing method

1986-12-29

1989-01-31

Smith, Jerry

Excavating

G01R 3128

Patent

active

048021636

ABSTRACT:
A test-facilitating circuit comprises a circuit of superior level in hierarchy constructed by connecting the circuit modules and taking out external nodes from predetermined circuit modules, an interposed gate provided for the input-output portions of each circuit module, an input gate an an output gate provided for a wiring between the interposed gates, with the mutual wiring as one of their ends, a device which connects the input terminal of an input gate to the input external node of the circuit module that does not belong to the circuit modules on the output side of the mutual wiring, a device which connects the output terminal of an output gate to the output external node of the circuit module that does not belong to the circuit modules on the input side of the mutual wiring, and a rewritable memory device provided for the control terminal of each interposed gate, input gate, and output gate. The test of a circuit module is carried out by selectively activating the interposed gate, input gate, and output gate that belong to the same circuit module, and by making use of the external nodes of other circuit modules connected to the external nodes and the input gate and the output gate that belong to the circuit module.

REFERENCES:
patent: 3783254 (1974-01-01), Eichelberger
patent: 4074851 (1978-02-01), Eichelberger
patent: 4519078 (1985-05-01), Komonytsky
patent: 4580137 (1986-04-01), Fiedler
patent: 4606024 (1986-08-01), Glass
patent: 4691161 (1987-09-01), Kant
patent: 4701921 (1987-10-01), Powell
IEEE 1985 Custom Integrated Circuits Conference, Toshiba Microcomputer Engineering Corp., (Nagao et al.), CH2157-6/85/0000-0267, p. 267 through 271, entitled "Super Integration".

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