Test detector/shutoff and method for BiCMOS integrated circuit

Details Test detector/shutoff and method for BiCMOS integrated circuit Test detector/shutoff and method for BiCMOS integrated circuit

1992-08-04

1994-03-15

Nguyen, Vinh

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, G01R 3128

Patent

active

052948838

ABSTRACT:
A test detect and shut off circuit for a BiCMOS integrated circuit is presented. The test detector/shutoff detects the presence of a predetermined test condition in the BiCMOS integrated circuit (IC), and upon detection of the predetermined condition isolates (i.e., switches off) the bipolar circuit portion from the CMOS logic portion of the BiCMOS IC. In this way, bias current in the bipolar transistor circuit is eliminated, thereby facilitating IDD testing of the BiCMOS logic. The detector/shutoff is particularly designed for BiCMOS implementations wherein a single voltage rail supplies voltage V.sub.DD to the logic and bipolar circuit portions of the IC. Corresponding test detect and circuit isolation methods are also presented.

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Gray, K. S. and Kosson, J. S., "Delay Margin Testing Circuit for CMOS Circuitry" in IBM Technical Disclosure Bulletin, vol. 29, No. 10, Mar. 1987.

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