Test data compression and decompression method using...

Details Test data compression and decompression method using... Test data compression and decompression method using...

2007-11-20

2007-11-20

Lu, Kuen S. (Department: 2167)

Data processing: database and file management or data structures

Database design

Data structure types

C707S793000, C707S793000

Reexamination Certificate

active

10867588

ABSTRACT:
A method of effectively compressing a test vector is introduced for testing a system-on-chip (SOC) semiconductor device. Since the number of test vectors is increased in a SOC, the number of ‘0’s is increased if adjacent test vectors are properly aligned using an ordering algorithm. ‘0000’ is considered as a single block and a counter of ‘0-group’ is incremented by one to encode each further instance of the string ‘0000’. A codeword capable of being decompressed can be generated using only a counter without using a memory block.

REFERENCES:
patent: 2004/0190331 (2004-09-01), Ross et al.
Gonciari et al.: “Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression”, Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition.
Li et al.: “Testing Data Compression Using Dictionaries with Selective Entries and Fixed-Length Indices”, ACM Transactions on Design Automation of Electronic Systems, vol. 8, No. 4, Oct. 2003.
Shi et al.: “FCSCAN: An Efficient Multiscan-based Test Compression Technique fro Test Cost Reduction”, Department of Computer Science, Waseda University, Japan, 2006.
Kay et al.: “Embedded Test Control Schemes for Compression in SOCs”, DAC 2002, Jun. 10-14, New Orleans, Louisiana, USA.

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