Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-04-05
2004-11-30
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06825682
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a test configuration for the functional testing of a semiconductor chip that can be subjected to a functional test for the purpose of checking the functionality of the semiconductor chip.
In the course of the fabrication of semiconductor chips, the latter are generally subjected to at least one functional test, in which the functionality of the semiconductor chip is checked. In this case, the semiconductor chip is tested for example by an external test device that generates test information and carries out the functional test. In this case, the test information is read into the semiconductor chip and compared with data that are read out.
A functional check of an integrated semiconductor memory, for example, is usually performed in a number of steps. In a first test configuration, functional tests are performed on unpackaged semiconductor chips which are usually disposed on semiconductor wafers (referred to as wafer test or wafer-level test). These tests generally take place in complex test systems in parallel for a plurality of semiconductor chips, in order to keep the test time short and the test costs low. In a further test configuration, functional tests are performed on the packaged semiconductor chip (referred to as a module test).
In semiconductor memories, the test time and the test complexity generally rise significantly as the storage density increases, and hence the test costs and also the fabrication costs increase. When an external test unit is used for a wafer test, test signals, control signals and operating voltage and/or operating current are generally fed via a limited number of drive channels by what is referred to as needle card technology (referred to as probe cards). In this case, the number of memory chips that can be tested in parallel is limited on account of mechanically dictated problems in needle card technology for example for feeding in the operating voltage.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a test configuration for the functional testing of a semiconductor chip which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which enables the test time and the test costs for a functional test to be carried out to be kept comparatively short and low, respectively.
With the foregoing and other objects in view there is provided, in accordance with the invention, a test configuration. The test configuration contains a support material and a semiconductor chip disposed on the support material. The semiconductor chip has a self-test unit generating test information for functionally checking the semiconductor chip. An energy source is provided which supplies an electrical energy supply from energy that is fed in contactlessly. The energy source is disposed on the support material and is connected to the semiconductor chip for providing the electrical energy supply to the semiconductor chip.
The object is achieved by the test configuration for the functional testing of the semiconductor chip. The semiconductor chip, which can be subjected to a functional test for the purpose of checking the functionality of the semiconductor chip is disposed on the support material. The semiconductor has a self-test unit for generating test information and for carrying out the functional test, and an energy source for providing an electrical energy supply from energy that is fed in contactlessly. The energy source is disposed on the support material and is connected to the semiconductor chip for the purpose of providing an energy supply for the semiconductor chip.
The test configuration according to the invention makes it possible to test with regard to functionality, in parallel, an, in principle, arbitrarily high number of semiconductor chips to be tested. The self-test unit makes it possible, independently of an external test unit, to generate test information and to carry out a functional test. Thus, it is not necessary for the semiconductor chip that is to be tested to be contact-connected to an external test device via external terminals for test or control signals. Moreover, since an energy source for providing an electrical energy supply from energy that is fed in contactlessly is disposed on the support material, for example a semiconductor wafer, and is connected to the semiconductor chip. Therefore, external terminals for feeding in an operating voltage and/or an operating current can, moreover, be obviated. As a result, the number of semiconductor chips to be tested in parallel is no longer limited on account of mechanically dictated problems as for example in needle card technology. The test costs and fabrication costs are additionally lowered since an external test unit is not required.
If a plurality of semiconductor chips are disposed for example on the semiconductor wafer, than it is possible to subject not only the semiconductor chips of the semiconductor wafer but also a plurality of semiconductor wafers, or their applied semiconductor chips, to a parallel functional test. This can be carried out as a contactless wafer test by the test configuration according to the invention.
In a development of the invention, the energy source has at least one solar cell for generating an operating current on the semiconductor chip by optical radiation that is fed in contactlessly. For this purpose, the solar cell is irradiated with visible light, for example, thereby generating a current flow that serves as an operating current on the semiconductor chip.
In a test configuration in which a plurality of semiconductor chips to be tested are applied on a semiconductor wafer, in one embodiment the solar cell is disposed in the scribe line of the semiconductor wafer. The scribe line separates the semiconductor chips on the semiconductor wafer from one another. In a later fabrication process, the semiconductor chips are separated from one another along the scribe line by the semiconductor wafer being sawn along the scribe line (referred to as dicing). The requisite space needed on the semiconductor wafer can be utilized in an advantageous manner by disposing the solar cell in the scribe line. Since the solar cell is no longer required for later operation of the semiconductor chip, it is unimportant that it is destroyed during the later process of sawing through the semiconductor wafer.
In order to achieve adequate current generation by the solar cell, a relatively large area is needed for the solar cell. The scribe line is necessarily enlarged because of this, which means that the number of semiconductor chips on the semiconductor wafer can generally be reduced. This disadvantage must be balanced against the saving in test costs.
In a further embodiment of the invention, the solar cell is disposed areally on a surface of the semiconductor wafer on which the semiconductor chip to be tested is applied. With a 100% photon yield of the solar cell, the latter can be applied directly to the semiconductor wafer or the semiconductor chip. However, if the solar cell is light-transmissive, then it is expedient for a radiation-absorbing layer to be applied between the solar cell and the semiconductor chip, in order to avoid charge carrier generation on the chip.
In a further embodiment of the invention, the solar cell is disposed on that surface of the support material which is remote from the semiconductor chip to be tested. Thus, if the solar cell is disposed on the rear side of the support material, for example a semiconductor wafer, then a plated-through hole is needed from the solar cell through the substrate of the semiconductor wafer to the other side of the semiconductor wafer. At the boundary between the plated-through hole and the support material or the semiconductor wafer, a current barrier in the form of a pn junction is disposed along the plated-through hole in order to avoid a current flow between the plated-through hole and the semiconductor wafer. In order that the plated-through hole is configured in a si
Kantz Dieter
Müller Jochen
Greenberg Laurence A.
Infineon - Technologies AG
Karlsen Ernest
Locher Ralph E.
Stemer Werner H.
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