Excavating
Patent
1995-06-07
1996-12-31
Beausoliel, Jr., Robert W.
Excavating
371 225, G11C 2900
Patent
active
055901344
ABSTRACT:
An integrated circuit includes read/write memory and non-memory circuitry. A detector generates a count of the number of bits of each data words recalled from the memory having a predetermined logic state. An adder accumulates the count for plural data words over a period of time into a count register. The integrated circuit may be tested by lading each data word of the read/write memory with a first logic state and repeatedly addressing said read/write memory circuitry with a predetermined number of each possible address in sequence. The resulting count in the count register is compared with an expected count. The integrated circuit may also be tested by loading a predetermined addressable storage location with another logic state while loading all other addressable storage locations with the first logic state and repeatedly addressing the predetermined addressable storage location. The resulting count in the count register is compared with another expected count. The non-memory circuitry is preferably digital to analog converters, whose outputs may be compared to test their operation.
REFERENCES:
patent: 3597199 (1971-05-01), Anderson et al.
patent: 3838264 (1974-09-01), Maker
patent: 4559626 (1985-12-01), Brown
Beausoliel, Jr. Robert W.
Donaldson Richard L.
Hua Ly V.
Kesterson James C.
Marshall, Jr. Robert D.
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