Test circuit with signature register and an additional register

Details Test circuit with signature register and an additional register Test circuit with signature register and an additional register

1990-11-01

1993-09-21

Atkinson, Charles E.

Excavating

371 221, G01R 3128

Patent

active

052475255

ABSTRACT:
A test circuit which utilizes a multi-bit impact signature register and an additional register coupled to the output of the signature register and configured as a linear feedback multi-stage shift register. The total number of stages in the two registers is larger than the width of the test data (number of bits) to be input. A single feedback loop couples the output of the last additional register stage back to the first stage of the signature register. Each bit of the test data is input to an exclusive-or element at the input to each stage of the shift register and is exclusive-or-operated sequentially with the result of an exclusive-or operation stored in the preceding stage, and the result of the operation in the last stage is fed from the additional register back to the first-stage exclusive-or- element of the signature register with a delay. Only one additional register having one or more stages is required for the hardware configuration while providing an error detecting rate of the same degree as the case of using a primitive polynomial, simplifying the actual circuit configuration, and reducing the occupying area on the chip.

REFERENCES:
patent: 4519078 (1985-05-01), Komonytsky
patent: 4594711 (1986-06-01), Thatte
patent: 4701916 (1987-10-01), Naven et al.
IEEE SC-15 No. 3, Jun. 1990, pp. 315-319.
Int. Test Conf., 1980; pp. 261-266.
Intl. Test Conf., 1981, pp. 15-20.
Intl. Solid-State Circuits Conf., Feb. 1982, pp. 60-61.
IEEE Test Conf., 1981, pp. 208-216.
IEEE C-29 No. 6, 1980, pp. 510-514.
IEEE Test Conf., 1986, pp. 282-288.
IEEE Test Conf., 1987, pp. 645-655.

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