Test circuit for testing semiconductor memory

Details Test circuit for testing semiconductor memory Test circuit for testing semiconductor memory

2001-06-21

2002-07-30

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S201000

Reexamination Certificate

active

06426912

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory of a multi-bit type which stores and outputs a plurality of bits at the same time, which form a multi-bit data.
2. Description of the Related Art
A digital system having a semiconductor memory such as a DRAM (Dynamic Random-Access Memory) has the following three features to increase the speed of transferring data.
First, the semiconductor memory is a multi-bit type which can store and output the bits forming a multi (×2
n
)-bit data (n is a natural number), at the same time.
Second, the semiconductor memory stores and outputs data in synchronism with an external clock signal supplied from a CPU (Central Processing Unit). The higher the frequency of the clock signal, the faster the memory (e.g., a SDRAM or a RDRAM) can store and output continuous data. Thus, the memory can serve to increase the speed of transferring data.
Third, the semiconductor memory incorporates a plurality of banks. The banks have identical elements each. The banks can store and output data, independently of one another. These measures taken, the time required to access the first data (known as “latency”) is short, thus enhancing the speed of transferring data.
FIG. 1
shows the layout of a conventional semiconductor memory. This memory has all three features mentioned above.
The conventional semiconductor memory comprises a memory chip
10
and four banks
11
-
0
to
11
-
3
provided in the chip
10
. Each of the banks
11
-
0
to
11
-
3
comprises a memory cell array and peripheral circuits such as a cell-array controller, a row address decoder, a column address decoder and a DQ buffer (i.e., a buffer provided in the input/output section of the bank).
The memory chip
10
has input/output region
12
. Provided in the data I/O region
12
are a plurality of input/output (I/O) circuits. For example, 16 I/O circuits are provided if the memory chip
10
is designed to store and output 16 bits (i.e., 16-bit data, or 2-byte data) at the same time.
The memory chip
10
also has a data bus
13
. The bus
13
extends between one block consisting of the first and second banks
11
-
0
and
11
-
1
and the other block consisting of the third and fourth banks
11
-
2
and
11
-
3
. The data bus
13
is designed to transfer data (e.g., 16-bit data) between each bank and the data I/O region
12
.
How the memory chip
10
stores and outputs multi-bit data will be explained.
First, one of the four banks
11
-
0
to
11
-
3
is selected. In the bank selected, the memory cell array is accessed on the basis of an address signal. As a result, 2
n
-bit (e.g., 16-bit data, or 2-byte data) is output from the bank. The 2
n
-bit data is supplied to the data I/O region
12
. The I/O region
12
outputs the data. Thus, the 2
n
-bit data is output from the memory chip
10
.
It is desired that the ratio of the region occupied by the data bus
13
to the all chip area be reduced as much as possible. In other words, the bus
13
needs to be made as thin as possible to decrease the chip area.
However, the greater the number of bits the chip
10
simultaneously store and outputs, the thicker the data bus
13
, and hence the larger the region the bus
13
occupies. More specifically, as the number of bits which the memory chip
10
can simultaneously store and output increases (from 16 bits to 32 bits and hence to 64 bits), the area of the memory chip
10
inevitably increases.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-mentioned problem inherent in the conventional semiconductor memory. Its object is to provide a semiconductor memory of multi-bit, clock-synchronized and multi-bank type which can transfer data at high speed, without having its chip area increased.
To achieve the object, a semiconductor memory according to a first aspect of the invention comprises a memory chip and a plurality of banks arranged on the memory chip, for storing and outputting multi-bit data, independently of one another.
Each of the banks has a plurality of memory-cell blocks, at least one column decoder, a plurality of row decoders, a plurality of DQ buffers, and a a cell-array controller.
Each of the memory-cell blocks comprises two sub-blocks, sense amplifiers, word lines, data lines and column-selecting line. Each sub-block is composed of one memory cell array. The sense amplifiers are located between the two sub-blocks. The word lines, data lines and column-selecting lines are arranged on the memory cell arrays constituting the two sub-blocks. The memory-cell blocks are paced apart along columns of memory cells and the column-selecting lines and data lines. The sub-blocks are spaced apart also along the columns of memory cells.
The column decoder is located at at least a first end of every column of memory cells. It is connected to the column-selecting lines.
The row decoders are located at a first end of every row of memory cells along which the word line extend, and are connected to the word lines. Each row decoder is provided for one memory-cell block.
The DQ buffers are located at a second end of every row of memory cells. Each DQ buffer is provided for one memory-cell block;
The cell-array controller is located at a second end of very row of memory cells, for controlling the reading and writing of the multi-bit data.
The semiconductor memory further comprises a data input/output region and a data bus. The data region is provided on the memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device. The data bus is provided for the plurality of banks, extends parallel to the columns of memory cells, for transferring multi-bit data between the plurality of banks, one the one hand, and the data input/output region, on the other.
Each bank has local DQ-line pairs and global DQ-line pairs. Each DQ-line pair is provided between the two sub-blocks of one memory-cell block and extends parallel to the rows of memory cells. The global DQ-line pairs extend over the memory-cell blocks, along the columns of memory cells. They connect the local DQ-line pairs to the DQ buffers.
A semiconductor memory according to a second aspect of the invention comprises a memory chip and a plurality of main banks. The main banks are arranged on the memory chip, for storing and outputting multi-bit data, independently of one another. Each main bank is composed of a plurality of sub-banks.
Each of the sub-banks comprises a plurality of memory-cell blocks, at least one column decoder, a plurality of row decoders, a plurality of DQ buffers, and a cell-array controller.
Each of the memory-cell blocks comprises two sub-blocks, sense amplifiers, word lines, data lines and column-selecting line. Each of the sub-blocks is composed of one memory cell array. The sense amplifiers is located between the two sub-blocks. The word lines, data lines and column-selecting lines are arranged on the memory cell arrays constituting the two sub-blocks. The memory-cell blocks are spaced apart along columns of memory cells and the column-selecting lines and data lines. The sub-blocks are spaced apart also along the columns of memory cells.
The column decoder is located at at least a first end of every column of memory cells. It is connected to the column-selecting lines.
The row decoders are located at a first end of every row of memory cells along which the word line extend. They are connected to the word lines. Each row decoder is provided for one memory-cell block.
The DQ buffers are located at a second end of every row of memory cells. Each DQ buffer is provided for one memory-cell block.
The cell-array controller is located at a second end of very row of memory cells, for controlling the reading and writing of the multi-bit data.
The semiconductor memory further comprises a data/input region and a plurality of data buses. The data input/output region is provided on the memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device. The

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