Test circuit for testing a three-state output buffer gate in a s

Details Test circuit for testing a three-state output buffer gate in a s Test circuit for testing a three-state output buffer gate in a s

1992-01-22

1993-04-27

Nguyen, Vinh

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, 371 151, G01R 3128

Patent

active

052065847

ABSTRACT:
A semiconductor integrated circuit provided with a test circuit for testing an output buffer (11) is disclosed. The test circuit is capable of transmitting a logic signal supplied from an internal circuit in a shorter transmission time than a conventional test circuit. Essential parts of the test circuit include a three-state input buffer (13) and a three-state buffer (14). In the test mode, buffer (14) takes a high-impedance state and buffer (13) transmits a test data signal (TSTD) supplied from an external circuit to output buffer (11) to be tested. In the output mode, buffer (13) takes a high-impedance state and buffer (14) transmits a logic signal supplied from an internal logic circuit to an external circuit through output buffer (11).

REFERENCES:
patent: 4782283 (1988-11-01), Zasio
patent: 5084874 (1992-01-01), Whetrel, Jr.

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