Test circuit for serial link receiver

Pulse or digital communications – Cable systems and components

Reexamination Certificate

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Reexamination Certificate

active

07940846

ABSTRACT:
A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

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P. Mollier et al., “Inter-chip noise reduction schematic for referenced receivers,” IBM Technical Disclosure bulletin FR886-0157, vol. 31, No. 2, Jul. 1988.

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