Test circuit for input-to-output speed measurement

Details Test circuit for input-to-output speed measurement Test circuit for input-to-output speed measurement

2003-05-13

2004-07-27

Pert, Evan (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C324S161000

Reexamination Certificate

active

06768333

ABSTRACT:

TECHNICAL FIELD
The present invention relates to testing of integrated circuit (IC) die or completed packages, and in particular to the measurement of input pin to output pin signal propagation speed.
BACKGROUND ART
One important measure in the testing of IC die and completed IC packages is the speed from an input pin through the chip to an output pin. It is important for quality control and meeting customer's specifications that the test equipment accurately measure this value.
FIG. 1
illustrates how this is usually done. A typical IC package
11
is laid out with pins or pads
15
surrounding the core circuitry
13
. An internal speed path
17
through the core
13
connects an input pad
19
to an output pad
21
, with a buffer element
20
in the circuit block
17
driving the output pad
21
. Probes
23
and
25
of the test equipment contact the pads
19
and
21
. The time it takes for a signal transition applied to the input pads
19
by the probe
23
to propagate to the output pad
21
and probe
25
is the speed data to be measured.
As IC technology migrates to lower signal voltages (5V, 3.3V, 2.5V, 1.8V, 1.5V, . . . ) and increases in speed, the input-to-output time becomes more difficult to measure accurately. When the time value goes below 3 ns, many testers cannot provide the required testing accuracy. Since the test probes need to contact the pads to make the measurement, the test set up itself adds load to the circuit being tested. The load that the testing equipment creates can slow down the data dramatically.
Thus, for example, an extra nanosecond is 20% for 5 ns part, but 33% for a 3 ns part. What is even worse, there can be considerable load variation between different test equipment units, producing uncertainty in the measurements.
An object of the present invention is to provide a test circuit integrated on the chip from which universal speed data that is accurate can be obtained.
DISCLOSURE OF THE INVENTION
The object is met by adding a D flip-flop to the speed path that registers the arrival at the output pad of a signal transition applied to the input pad. This flip-flop is clocked at variable clock-speed, so that at some higher clock frequencies, the transition has not yet arrived in time to be registered, while at lower clock frequencies, the transition is registered by the flip-flop. One-half the clock period that just registers the transition corresponds to the input-to-output delay time.


REFERENCES:
patent: 5818250 (1998-10-01), Yeung et al.
patent: 6219305 (2001-04-01), Patrie et al.

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