Test circuit for imaging sensing integrated circuits

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor

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Details

324537, 324501, G01R 2726

Patent

active

052764001

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

This invention relates to the testing of integrated circuits for image sensing. The invention may be applied to array sensors sensitive to visible and infra-red radiation and to other forms of radiation.


BACKGROUND OF THE INVENTION

Integrated circuit array sensors are difficult to test in production. The desired result is that each sensing site (pixel) should be responsive to the anticipated radiation and should be capable of storing an analogue charge packet for a suitable integration period. This charge packet should then be readable by activating word-lines to enable a row of pixels to be sensed via bit-lines which connect the pixels to sense amplifiers or to other readout mechanisms at the edge of the sensing array. A typical architecture has horizontal scan-circuit, which controls the read-out of analogue switches or sensors, connected to an output amplifier and buffer.
A complete optical test is awkward to perform when the integrated circuits are in wafer form. It is more convenient to perform this test once the circuits have been separated and packaged. However, it is economically desirable only to package good circuits or those circuits which are most likely to pass the final test. It is possible to assess circuits in the wafer by a preliminary electrical test of the array. This test may include writing charge packets into pixel locations and then executing sensing procedures to determine whether each pixel has successfully stored a packet and whether the word and bit-line mechanisms can successfully access each location. Unfortunately, this can be a long procedure and it is made more difficult if the test includes the analog characteristics of each pixel.
Both the final optical test and the on-wafer electrical test can require specialized test equipment and occupy test times longer than those associated with conventional digital integrated circuit production.


SUMMARY OF THE INVENTION

An object of the present invention is to obviate or mitigate at least one of the aforementioned problems.
This is achieved by recognizing that fabrication of such image sensor arrays results in faults within the pixel sites which are rare and physically scattered. This is largely a result of the very small area of each pixel (typically less than 400 sq. microns) and the yield characteristics of contemporary fabrication processes. Internal faults of this nature in individual pixels are likely to fall within the criterion of product acceptability.
It is, therefore, deduced that catastrophic sensor faults are likely to occur in the word lines, bit-lines or peripheral circuits connected to them. Typically, a word or bit-line fault (an open-circuit failure) will cause a row or column of the sensed image to be in error and faults of this nature are generally not acceptable.
Thus, a solution is achieved by concentrating and testing the integrity of word and bit lines and their associated circuitry using tests that are entirely digital in a conventional sense of digital integrated circuit technology. However, the solution also permits the testing of individual sensing sites. These tests may therefore be performed by equipment and procedures normally used for volume integrated circuit production.
According to one aspect of the present invention there is provided an image sensing integrated circuit (IC) having a sensor array comprising a multiplicity of radiation sensing sites, a plurality of word-lines and a plurality of bit-lines, each sensing site being capable of storing an analog charge packet for a predetermined period, said sensor array being coupled on-board to signal read-out means for providing an output signal from said sensor array, said sensor array being coupled to on-board digital test circuit means disposed at the periphery of the array, said on-board digital test circuit means being responsive to a control signal to generate a digital test signal for testing the integrity of at least one of a plurality of the sensor array bit-lines and a plurality of the sensor array word-lines in

REFERENCES:
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patent: 4894605 (1990-01-01), Ringleb et al.
patent: 5012185 (1991-04-01), Ohfuji
patent: 5057775 (1991-10-01), Hall
Proceedings of the IEEE 1989 Custom Integrated Circuits Conference 15-18 May 1989, San Diego, Calif. IEE. Nigh et al. "A Self-Testing ALU Using Built-In Current Sensing" see pp. 2211-2214.
Optical Engineering, vol. 21, No. 5 Sep.-Oct. 1982 Dereniak et al. "Microprocessor-Based Charge Coupled Device (CCD) Test Console." see pp. 942-944.
Asano, Solid State Sensors Continue to Improve Their Image, 11-1988, pp. 64-67, JEE.-Journal of Electronic Engineering No. 263, Tokyo, Japan.

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