Test circuit arrangement and method for testing a...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S765010

Reexamination Certificate

active

06873173

ABSTRACT:
The invention relates to a test circuit configuration. Every gate terminal of a transistor to be tested is coupled to a gate voltage source in such a manner that the gate voltage can be measured and adjusted individually on every gate terminal. The source terminal of every transistor to be tested can be coupled to the source voltage source in such a manner that the source voltage can be measured and adjusted individually on every source terminal.

REFERENCES:
patent: 4972144 (1990-11-01), Lyon et al.
patent: 5223792 (1993-06-01), El-Ayat et al.
patent: 6489798 (2002-12-01), Scott-Thomas et al.
patent: 692 17 827 (1993-05-01), None
C. Linnenbank et al., What Do Matching Results of Medium Area MOSFETs Reveal for Large Area Devices in Typical Analog Applications? Proceedings of the 28thEuropean Solid-State Device Research Conference, ESSDRC 1998, Bordeaux, France, pp. 104-107, Sep. 8-10, 1998.
M. Eisele et al., Intra-Die Device Parameter Variations and Their Impact on Digital CMOS Gates at Low Supply Voltages, IEEE, IEDM 1005, pp. 67-70, 1995.
K. R. Lakshmikumar et al., Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design, IEEE Journal of Solid-State Circuits, vol. SC-21, No. 6, pp. 1057-1066, Dec., 1986.
M.J.M. Pelgrom et al., Transistor Matching in Analog CMOS Applications, IEEE, International Electron Devices Meeting, San Francisco, CA, IEDM 98, pp. 915-918, Dec. 6-9, 1998.
K. Goser, MOS Transistors as High-speed switches in a Selection Matrix, NTZ, lllue 10, pp. 512-521, 1970.
Thewes R et al., On the Matching Behavior of MOSFET Small Signal Parameters, Proceedings of the 2000 International Conference on Microelectronic Test Structures, pp. 137-141, Mar. 13-16, 2000.
Portmann L. et al., A High Density Integrated Text Matrix of MOS Transistors for Matching Study, Proc. IEEE 1998 Int. Conference on Microelectronic Test Structures. vol. 11, Mar. 1998.
Thewes, R. et al., Explanation and Quantitative Model for the Matching Behavior of Poly-Silicon Resistors. International Electron Devices Meeting 1998. IEDM Technical Digest. San Francisco, CA, Dec. 6-9, 1998, pp. 98-771-774.
Chong-Fun Yu et al., An Accurate and Matching-Free Threshold Voltage Extraction Scheme for MOS Transistors. Circuits and Systems, 1994. 1994 IEEE Intl. Symposium, London UK, May 30-Jun. 2, 1994, pp. 115-118.

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