Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-02-05
2004-07-20
Tang, Minh N. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06765403
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to an integrated circuit and to testing of the operationality of multiple power supply connections to such an integrated circuit.
BACKGROUND OF THE INVENTION
Modern integrated circuits often have a considerable number of external power supply pins for the same power supply voltage. This plurality of power supply pins poses a problem during circuit test, because malfunctioning of a part of the power supply pins does not normally show up in tests of circuit functionality.
From U.S. Pat. No. 5,068,604 it is known to test the operationality of multiple power supply connections for the same supply voltage of an integrated circuit by observing the voltage drops along power supply conductors. For this purpose, a current drawing circuit is activated that draws a substantial current from the power supply to create an observable voltage drop.
Thus, the power supply connections can be tested both inside the integrated circuit and outside the integrated circuit, for example on a printed circuit board on which the integrated circuit is mounted.
Generally, too many current drawing circuits should not be activated all at the same time. Each current drawing circuit draws a considerable current to create an observable voltage drop. Activating all or too many current drawing circuits at the same time could damage the integrated circuit due to the large resulting currents and/or power dissipation. Supply pins should be tested only one or a few at a time, activating only a few current drawing circuits that are connected to the power supply conductor near the location where the pin or pins under test is or are connected to that power supply conductor.
The operation of the known test circuit is controlled by commands entered through a boundary scan interface. The commands control the activation of the current drawing circuits, and they should ensure that not too many current drawing circuits are activated at the same time. However, if the control interface does not operate properly, for example due to the very faults in the power supply connection, or because of errors in the commands, too many current drawing circuits might be activated simultaneously, causing damage to the integrated circuit.
SUMMARY OF THE INVENTION
Amongst others, it is an object of the invention to protect the integrated circuit against damage from activation of too many current drawing circuits at the same time.
The invention provides for an integrated circuit that comprises
a plurality of power supply pads;
a power supply conductor;
a plurality of power supply connections, each coupled between the power supply conductor and a respective one of the power supply pads at a respective location along the power supply conductor;
current test circuitry for performing detections, each of a voltage drop between a first and second point along a respective one of the power supply connections;
switchable test current drawing circuits coupled in parallel at respective further locations along the power supply conductor;
a test circuit, arranged to cause the current test circuitry to perform said detections successively, each while activating at least a respective one of the current drawing circuits, keeping inactive at least a further respective one of the current drawing circuits that is connected to the power supply conductor further from the respective one of the power supply connections on which that detection is performed than the activated respective one of the current drawing circuits.
Thus only one or more current drawing circuits close to the power supply connection under test will be activated. Current drawing circuits further from the power supply connection under test are not active when that power supply connection is tested. This prevents damage to the integrated circuit due to excessive power dissipation.
In an embodiment the test circuit comprises a functional chain of signal lines, each specific to a respective one of the detections, each for carrying a signal responsive to completion of activation of the current drawing circuit that is activated during the respective one of the detections, at least when that detection has indicated no failure, the test circuit controlling activation of the respective ones of the current drawing circuits for successive detections with signals from successive ones of the signal lines from the chain.
Thus it is ensured by a handshake mechanism that a first and second subset of current drawing circuits that are used to test different power supply connections cannot be activated simultaneously even if there are errors. This is realized by using separate signal lines for different current drawing circuits and ensuring that a set of current drawing circuits can only be activated when the signal line of the preceding set indicates that that preceding subset has been de-activated.
In an embodiment of the integrated circuit according to the invention the test circuit is triggered by a reset of the circuit, for example a power-on reset or another type of reset. Thus, the test of the power supply connections can be performed before any other test, even without loading a scan chain. Power supply faults, which might lead to erroneous results in other tests can thus be detected before these other tests are performed.
In another embodiment of the integrated circuit according to the invention, activation of a subset of the current drawing circuits is triggered by an indication that a test using a previous subset of current drawing circuits has detected no failure. Thus, no additional signal lines are needed to sequence the activation of different subsets of the current drawing circuits. If one of the tests indicates a failure, no further tests are performed, additionally reducing the risk of damage.
REFERENCES:
patent: 5068604 (1991-11-01), Van de Lagemaat
patent: 5801536 (1998-09-01), Brambilla et al.
patent: 0647905 (1995-04-01), None
patent: WO0163310 (2001-08-01), None
De Jong Franciscus Gerardus Maria
De Wilde Johannes
Den Besten Gerrit Willem
Schuttert Rodger Frank
Koninklijke Philips Electronics , N.V.
Tang Minh N.
Ure Michael J.
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