Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2005-08-16
2005-08-16
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C714S047300
Reexamination Certificate
active
06931344
ABSTRACT:
A test circuit is incorporated in a device having an output circuit for outputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test output buffer connected in parallel with output nodes of the output circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the output nodes, and the test output buffer receives test data from the test data generating circuit and outputs the test data to the output nodes. Similarly, a test circuit is incorporated in a device having an input circuit for inputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test input buffer connected in parallel with input nodes of the input circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the input nodes, and the test input buffer receives test data from the test data generating circuit and inputs the test data to the input nodes.
REFERENCES:
patent: 4698830 (1987-10-01), Barzilai et al.
patent: 4855669 (1989-08-01), Mahoney
patent: 5287386 (1994-02-01), Wade et al.
patent: 5299136 (1994-03-01), Babakanian et al.
patent: 5598541 (1997-01-01), Malladi
patent: 5706297 (1998-01-01), Jeppesen et al.
patent: 6304987 (2001-10-01), Whetsel, Jr.
patent: 6349398 (2002-02-01), Resnick
patent: 6578180 (2003-06-01), Tanner
patent: 6629297 (2003-09-01), Ganesan et al.
“Integration of IEEE 1149.1 with Mixed ECL, TTL, and Differential Logic Signals”, John Andrews, 1993 IEEE, pp. 355-360.
“Built-In Parametric Test For Controlled Impedance I/Os”, Tord Haulin, 1997 IEEE, pp. 123-128.
Aoyagi Koji
Gotoh Kohtaroh
Nishio Shigeru
Terashima Kazuhiro
Arent & Fox PLLC
Fujitsu Limited
Hoff Marc S.
Raymond Edward
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