Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
1998-11-12
2001-04-03
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S118000
Reexamination Certificate
active
06211803
ABSTRACT:
This invention relates to a test circuit and method for testing Analog to Digital Converters (ADCs), and more particularly, to a test circuit and method for measuring switching point voltages, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) of ADCs.
BACKGROUND OF THE INVENTION
Analog to digital converters (ADCs) are used in many electronics applications. Complex ADCs can convert analog signals into an N-bit binary-encoded digital value, and comprise hundreds or thousands of transistors and other passive elements. Other ADCs are as simple as, e.g., a 7-transistor comparator or 2-transistor logic inverter. Herein, N is a positive integer.
A key parameter of interest for any ADC is the voltage above which a specific digital output is generated, and below which a different digital output is generated. This value is commonly referred to as a switching point voltage, V
SW
, and is illustrated graphically in
FIG. 1
b.
For 1-bit converters, such as a logic gate
20
shown in
FIG. 2
a
, the switching point voltage V
SW
is typically mid-way between the power supply voltage (V
DD
or V
CC
) and ground (V
SS
or Gnd) as shown in
FIG. 2
b
. In a logic gate,
20
the switching point voltage V
SW
is also called a logic threshold.
A comparator
30
shown in
FIG. 3
a
is also a 1-bit converter. The comparator
30
has a non-inverting input
32
and an inverting input
34
. As shown in
FIG. 3
b
, the switching point voltage V
SW
for either input
32
,
34
of the comparator
30
is approximately equal to the adjustable DC voltage V
DC
36
connected to the other input
34
,
32
of the comparator
30
.
For N-bit converters whose digital output is N bits wide, there are 2
N
−1 switching point voltages, one between each of the 2
N
possible voltage ranges corresponding to a unique digital output code. The voltage difference between each measured switching point voltage V
SW
and the ideal switching point voltage V
SW
is the INL. All of the 2
N
voltage ranges, or step sizes, should be equal except the first and last ranges; the difference between any step and the ideal step size is referred to as the DNL. DNL and INL are key measures of an ADC's quality. For example, in a 2-bit ADC
10
shown in
FIG. 1
a
, there are 3 switching point voltages V
SW1
, V
SW2
and V
SW3
as shown in
FIG. 1
b
. The DNL of the ADC
10
is the difference between the ideal step size (V
max
−V
min
)/(2
N
−1) and each voltage range: between V
SW1
and V
SW2
14, and between V
SW2
and V
SW3
16; the first and last ranges 12 and 18 are not counted. DNL having the largest deviation from the ideal value is reported as the maximum DNL.
Conventionally, when N is less than 10, the switching point voltage V
SW
is measured by ramping the input voltage to an ADC relatively slowly from a low value to a high value, and recording the voltage at which the digital output of the ADC suddenly changes state. When N is 10 or larger, this test method is often impractical because of noise. For example, for a 5 volt full-scale input range and 10 bits resolution, each of the 1024 voltage ranges is only 5/1023=4.88 millivolts wide. Peak-to-peak noise can easily exceed this voltage width in a test environment. An alternative method, in this case, is to record a histogram of the output digital codes for an adjustable DC voltage input, and to then record each input voltage for which the histogram has a mean equal to each digital output code. This measurement method requires generation of very accurate voltages by the tester, and is relatively slow.
Another method is to provide a stimulus waveform comprising an asynchronous, periodic linear ramp, and to record the histogram for all output values from the ADC—ideally each bin of the histogram will contain the same count, so deviations indicate non-linearity. This method requires a very linear stimulus and a significant amount of digital storage, e.g. 2
N+6
bits provide 2
N
bins with a maximum bin count of 2
6
=64, which equals 64K bits for a 10-bit ADC.
A sigma-delta (or delta-sigma) ADC is able to achieve many bits of resolution and yet a single-order converter uses only a single comparator and analog integrator. One implementation of the front-end
40
of such a converter is shown in
FIG. 4
a
. The front end circuit
40
comprises a flip-flop
42
receiving a clock signal, and an analog integrator including two resistors
44
and
46
having resistance R
1
and R
2
and a capacitor
48
having capacitance C. When an input voltage V
in
to the circuit
40
is not equal to the switching point voltage V
SW
of the ADC, the voltage V
C
changes with the waveform like line
49
a
shown in
FIG. 4
b
. The output of the circuit
40
changes with the waveform like line
49
c
. The clock signal is shown in line
49
b
. One possible implementation of such a sigma-delta ADC is disclosed in U.S. Pat. No. 4,009,475 issued February, 1977 to DeFreitas. In the output signal D
out
, the proportion of ones, or zeroes, in a selected number of clock cycles is linearly related to the input voltage V
in
and to the resistance ratio R
1
/R
2
of the resistors
44
and
46
, but is insensitive to the capacitance C of the capacitor
48
. The circuit
40
is a front end of an ADC, and not a testing device for measuring the switching point voltage.
FIG. 5
shows a circuit
50
disclosed in U.S. Pat. No. 4,503,465 issued March, 1985 to Wine. The circuit
50
generates a bias voltage V
b
at the input to a logic gate
52
which is equal to the switching point voltage V
SW
of the logic gate
52
. The circuit
50
uses digital circuitry
54
plus a resistor
56
having resistance r
4
and a capacitor
58
having capacitance C
b
. The circuit
50
is a digital implementation of an analog signal comparator, comparing V
in
to reference voltage V
ref
. This is a comparator or converter, and not a testing device for measuring the switching point voltage as a means of testing the circuit.
A method for measuring DNL for an ADC is disclosed by Arabi and Kaminska in IEEE ITC'97 Proceedings, pp. 786-95, and shown in
FIG. 6. A
circuit
60
is disclosed in which the output of a self-timed ADC
62
is compared to two digital references by a control logic circuit
64
. The result of the comparison is connected to a current source/sink circuit
66
which is connected to a source voltage V
DD
and a sink voltage V
SS
. The output of the current source/sink circuit
66
drives a capacitor
68
having capacitance C and the input of the ADC
62
. The circuit
60
oscillates at a frequency f
OSC
. The oscillation period minus four times the conversion period of the ADC
62
, times the source/sink current value I
souce
/I
sink
, divided by twice the capacitance C, is equal to the voltage step that the two digital references represent. However, in this method, the measurement is dependent on the capacitance C and current of the current source/sink circuit
66
, and the conversion time of the ADC.
It is therefore desirable to provide a circuit for measuring switching point voltages, INL and DNL of an ADC, which is simple and independent of the conversion time of the ADC, and independent of the exact value of the resistance R and capacitance C.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a circuit for measuring switching point voltages, INL and DNL of an ADC, which is simple and independent of the exact values and delays of the components used.
To this end, the present invention uses negative feedback to an analog input voltage of the ADC so as to keep the analog input voltage as close as possible to a switching point voltage of the ADC.
In accordance with an aspect of the present invention, there is provided a test circuit for measuring a switching point voltage of an N-bit analog-to-digital converter (ADC) having an analog input and a digital output. The test circuit comprises a digital feedback circuit, an analog averaging circuit and a digital averaging circuit. The digital feedback circuit samples a digital value from the digital ou
LogicVision, Inc.
Skjerven Morrill & MacPherson LLP
Wamsley Patrick
LandOfFree
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