Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1992-07-23
1994-07-12
Wieder, Kenneth A.
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324 731, G01R 1512
Patent
active
053292286
DESCRIPTION:
BRIEF SUMMARY
This invention relates to a semiconductor test chip for use in semiconductor fabrication fault analysis.
Semiconductor integrated circuits, or chips as they are commonly known, which fulfil a variety of functions are now in widespread use. They are fabricated by selectively implanting impurities into, and applying conductive and insulating layers onto, a semiconductor, for example silicon, substrate. Each chip may contain a large number of components co-operating to fulfil a predetermined function.
Semiconductor chips are not manufactured individually, but rather as an assembly of a hundred or more chips on a "wafer", which is then divided up to produce the individual chips. An ongoing problem in the manufacture of semiconductor chips has to do with yield. Because of various faults that can occur in fabrication of a wafer, a significant number of the chips have to be discarded for one reason or another, thereby driving up the cost of the individual chips. An ongoing objective is to improve manufacturing techniques to increase the percentage yield per wafer and thereby drive down the unit costs.
In order to improve manufacturing techniques, and thereby increase yield, it is necessary to learn more about the defects that occur in the manufacturing process. A number of sophisticated techniques, such as on-line yield modelling, are available for this purpose. The present invention constitutes an important tool in the application of these techniques by allowing studies to be carried out on the specific types of defects occurring in semiconductor test chips for any given manufacturing process. When changes are made to a manufacturing process, the process can be used to manufacture a wafer containing test chips according to the invention, thereby permitting the type and number defects induced by the process to be studied. From this data improvements to the manufacturing process can be implemented.
Test chips have been employed for many years. However, while in the prior art while such chips have been able to identify defective cells, they have not been able to physically identify the defect within a particular cell. This latter operation must be done manually with the aid of, for example, optical, scanning, or transmission electron microscopes.
U.S. Pat. No. 4,719,411 to Buehler, issued Jan. 12, 1988, describes set of addressable test structures, each of which uses addressing schemes to address individual elements of the structure in a matrix. In Buehler, the addressable elements consist of invertor/transmission gate cells connected to an array of probe pads. By taking measurements of the output voltage, defective cells can be identified. Buehler does not permit the physical nature of the faults within the cells to be determined.
U.S. Pat. No. 4,835,466 to Maly et al, issued May 30, 1989, describes a meander structure applied to a semiconductor substrate. By measuring the resistance between points on the meander, faulty points can be identified. As is the case in Buehler, the electrical measurements do not give detailed information about the physical nature of the faults within the cells. Also as the structure of Maly's chip is not representative of practical active devices, the results are of questionable validity for application to real working chips.
Other prior art patents dealing with faulty cell identification are U.S. Pat. No. 4,801,869 to Sproggis, U.S. Pat. No. 4,782,288 to Vinto, U.S. Pat. No. 4,739,388 to Packeiser et al, and U.S. Pat. No. 4,654,872. None of these patents discloses an apparatus for determining the physical nature of the defects present within a faulty cell.
An object of the present invention is to alleviate the aforementioned disadvantages of the prior art.
According to the present invention there is provided a semiconductor test chip for use in semiconductor fabrication fault analysis, comprising an n x m array of transmission gate cells arranged such that within a given row respective strips of conductive material of a first type form common source and drain electrodes for the transi
REFERENCES:
patent: 4404519 (1983-09-01), Wescott
patent: 4719411 (1988-01-01), Buehler
patent: 4835466 (1989-05-01), Maly et al.
patent: 4961192 (1990-08-01), Grimes
Bowser B.
Mitel Corporation
Wieder Kenneth A.
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